CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 14, 1999
4241V
Features
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (I
CC
= 20 mA)
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V tolerant inputs V
IH max
= 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width expansion capability
• Space saving 32-pin 7 mm x 7 mm TQFP
• 32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. Programmable features include Almost Full/Al-
most Empty flags. These FIFOs provide solutions for a wide
variety of data buffering needs, including high-speed data ac-
quisition, multiprocessor interfaces, and communications buff-
ering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled
in a similar manner by a Free-Running Read Clock (RCLK)
and two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock fre-
quencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data
.
Logic Block Diagram
Pin Configuration
42X1V–1
42X1V–2
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
−
8
RCLK
EF
PAE
PAF
Q0
−
8
WEN1
WCLK
RS
OE
Dual Port
RAM Array
64 x 9
8Kx 9
WEN2/LD
REN1 REN2
FF
PLCC
42X1V–3
D
1
D
0
RCLK
V
CC
D
8
D
7
D
6
D
5
D
4
D
3
GND
WCLK
WEN2/LD
Q
8
Q
7
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
REN1
OE
REN2
4 3 2 1
31 30
32
D
1
D
0
RCLK
GND
PAF
PAE
REN1
REN2
21
22
23
24
27
28
29
25
26
14151617 181920
17
18
19
20
21
22
23
24
14 15 16
9 10 11 12 13
31 30
32
29 28 27
25
26
Q
6
Q
5
WEN1
RS
FF
Q
0
Q
1
Q
2
Q
3
Q
4
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
EF
OE
V
CC
WCLK
WEN2/LD
Q
8
Q
7
Q
6
Q
5
WEN1
RS
TQFP
Top View
Top View
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
2
Functional Description
(continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty
−
7 and Full
−
7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags de-
noting Almost Full and Full states are updated exclusively by
WCLK. The synchronous flag architecture guarantees that the
flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65
µ
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
CY7C42X1V-15
CY7C42X1V-25
CY7C42X1V-35
Maximum Frequency (MHz)
66.7
40
28.6
Maximum Access Time (ns)
11
15
20
Minimum Cycle Time (ns)
15
25
35
Minimum Data or Enable Set-Up (ns)
4
6
7
Minimum Data or Enable Hold (ns)
1
1
2
Maximum Flag Delay (ns)
10
15
20
Active Power Supply
Current (mA)
Commercial
20
20
20
CY7C4421V
CY7C4201V
CY7C4211V
CY7C4221V
CY7C4231V
CY7C4241V
CY7C4251V
Density
64 x 9
256 x 9
512 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Pin Definitions
Signal Name
Description
I/O
Description
D
0
−
8
Data Inputs
I
Data Inputs for 9-bit bus.
Q
0
−
8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Load
I
REN1, REN2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset
register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO.
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
....................................... −
65
°
C to +150
°
C
Ambient Temperature with
Power Applied
.................................................... −
55
°
C to +125
°
C
Supply Voltage to Ground Potential
..................−
0.5V to +5.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−
0.5V to +5.0V
DC Input Voltage
.................................................−
0.5V to +5.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Pin Definitions
(continued)
Signal Name
Description
I/O
Description
Operating Range
Range
Ambient Temperature
V
CC
Commercial
0
°
C to +70
°
C
3.3V
±
300mV
Electrical Characteristics
Over the Operating Range
7C42X1V-15
7C42X1V-25
7C42X1V-35
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
=
−
2.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.0
5.0
2.0
5.0
2.0
5.0
V
V
IL
Input LOW Voltage
−
0.5
0.8
−
0.5
0.8
−
0.5
0.8
V
I
IX
Input Leakage
Current
V
CC
= Max.
−
10
+10
−
10
+10
−
10
+10
µ
A
I
OZL
I
OZH
Output OFF,
High Z Current
OE > V
IH
,
V
SS
< V
O
< V
CC
−
10
+10
−
10
+10
−
10
+10
µ
A
I
CC
[1]
Active Power Supply
Current
Com’l
20
20
20
mA
I
SB
[2]
Average Standby
Current
Com’l
6
6
6
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
5
pF
C
OUT
Output Capacitance
7
pF
Notes:
1.
Outputs open. Tested at Frequency = 20 MHz.
2.
All inputs = V
CC
– 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
3.
Tested initially and after any design or process changes that may affect these parameters.
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
4
AC Test Loads and Waveforms
[4, 5]
3.0V
3.3V
OUTPUT
R1= 330
Ω
R2=510
Ω
C
L
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
OUTPUT
Vth=2.0V
Equivalent to:
THÉ VENIN EQUIVALENT
42X1V–4
Rth=200
Ω
ALL INPUT PULSES
42X1V–5
Switching Characteristics
Over the Operating Range
7C42X1V-15
7C42X1V-25
7C42X1V-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
S
Clock Cycle Frequency
66.7
40
28.6
MHz
t
A
Data Access Time
2
11
2
15
2
20
ns
t
CLK
Clock Cycle Time
15
25
35
ns
t
CLKH
Clock HIGH Time
6
10
14
ns
t
CLKL
Clock LOW Time
6
10
14
ns
t
DS
Data Set-Up Time
4
6
7
ns
t
DH
Data Hold Time
1
2
2
ns
t
ENS
Enable Set-Up Time
4
6
7
ns
t
ENH
Enable Hold Time
1
2
2
ns
t
RS
Reset Pulse Width
[6]
15
25
35
ns
t
RSS
Reset Set-Up Time
10
15
20
ns
t
RSR
Reset Recovery Time
10
15
20
ns
t
RSF
Reset to Flag and Output Time
18
25
35
ns
t
OLZ
Output Enable to Output in Low Z
[7]
0
0
0
ns
t
OE
Output Enable to Output Valid
3
8
3
12
3
15
ns
t
OHZ
Output Enable to Output in High Z
[7]
3
8
3
12
3
15
ns
t
WFF
Write Clock to Full Flag
11
15
20
ns
t
REF
Read Clock to Empty Flag
11
15
20
ns
t
PAF
Clock to Programmable Almost-Full Flag
18
15
20
ns
t
PAE
Clock to Programmable Almost-Full Flag
18
15
20
ns
t
SKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
6
10
12
ns
t
SKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
15
18
20
ns
Notes:
4.
C
L
= 30 pF for all AC parameters except for t
OHZ
.
5.
C
L
= 5 pF for t
OHZ
.
6.
Pulse widths less than minimum values are not allowed.
7.
Values guaranteed by design, not currently tested.
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
5
Switching Waveforms
Notes:
8.
t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK rising edge.
9.
t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then EF may not change state until the next RCLK rising edge.
Write Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
DS
t
SKEW1
t
ENS
WEN1
t
CLK
t
DH
t
WFF
t
WFF
t
ENH
WCLK
D
0
–D
8
FF
REN1,REN2
RCLK
42X1V–6
NO OPERATION
WEN2
(if applicable)
[8]
REN1,REN2
Read Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
SKEW1
WEN1
t
CKL
t
OHZ
t
REF
t
REF
RCLK
Q
0
–Q
8
EF
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
42X1V–7
WEN2
[9]
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
6
Notes:
10. The clocks (RCLK, WCLK) can be free-running during reset.
11. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
12. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
Switching Waveforms
(continued)
t
RS
t
RSR
Q
0
−
Q
8
RS
t
RSF
t
RSF
t
RSF
O
E
=1
OE=0
REN1,
REN2
EF,PAE
FF,PAF,
42X1V–8
t
RSS
t
RSR
t
RSS
t
RSR
t
RSS
WEN2/LD
WEN1
Reset Timing
[10]
[12]
[11]
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
7
Notes:
13. When t
SKEW1
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW1
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
14. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms
(continued)
D
0 (FIRSTVALID WRITE)
First Data Word Latency after Reset with Simultaneous Read and Write
t
SKEW1
WEN1
WCLK
Q
0
–Q
8
EF
REN1,
REN2
OE
t
OE
t
ENS
t
OLZ
t
DS
RCLK
t
REF
t
A
t
FRL
D
1
D
2
D
3
D
4
D
0
D
1
D
0
–D
8
42X1V–9
t
A
WEN2
(if applicable)
[13]
[14]
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
8
Switching Waveforms
(continued)
DATAWRITE2
DATAWRITE1
t
ENS
t
SKEW1
DATA IN OUTPUT REGISTER
Empty Flag Timing
WEN1
WCLK
Q
0
–Q
8
EF
REN1,
REN2
OE
t
DS
t
ENH
RCLK
t
REF
t
A
t
FRL
D
0
–D
8
DATA READ
t
SKEW1
t
FRL
t
REF
t
DS
t
ENS
t
ENH
42X1V–10
t
ENS
WEN2
(if applicable)
t
ENH
t
ENS
t
ENH
t
REF
LOW
[13]
[13]
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
9
Notes:
15. t
SKEW2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than t
SKEW2
, then PAE may not change state until the next RCLK.
16. PAE offset = n.
17. If a read is performed on this rising edge of the read clock, there will be Empty + (n
−
1) words in the FIFO when PAE goes LOW.
Switching Waveforms
(continued)
Full Flag Timing
Q
0
–Q
8
REN1,
REN2
WEN1
WEN2
(if applicable)
D
0
–D
8
NEXT DATA READ
DATA WRITE
NO WRITE
DATA IN OUTPUT REGISTER
FF
WCLK
OE
RCLK
t
A
DATA READ
t