PRELIMINARY
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO w/Bus Matching
CY7C4808V25
CY7C4806V25
CY7C4804V25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 18, 2000
sure
0251
Features
• High-speed, low-power, unidirectional, first-in first-out
(FIFO) memories w/bus matching capabilities
• 64K x 80 (CY7C4808V25)
• 16K x 80 (CY7C4806V25)
• 4K x 80 (CY7C4804V25)
• 2.5V ± 100 mV power supply
• All I/Os are 1.5V HSTL
• Individual clock frequency up to 200 MHz (5 ns
read/write cycle times)
• High-speed access with t
A
= 3.3 ns
• Bus matching on both ports: x80, x40, x20, x10
• Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
• CY standard or First-Word Fall-Through modes
• Serial and parallel programming of Almost Empty/Full
flags, each with 3 default values (8, 16, 64)
• Master and Partial reset capability
• Retransmit capability
• Big or Little Endian format on Port B
• 288 FBGA 19 mm x 19 mm (1.0-mm ball pitch) packaging
• Width and depth expansion capability
• Fabricated using Cypress 0.21-micron CMOS Technol-
ogy for optimum speed/power
Preliminary Top Level Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Bus
M
a
tc
hi
ng I
n
p
u
t Regi
st
e
r
Bus
M
a
tc
hi
ng Out
p
u
t Regi
st
er
Dual Ported
Status
Flag Logic
Programmable Flag Offset Registers
4K/16K/64Kx80
FIFO
CLKA
CSA
ENA
MR
PR
FF/IR
AF
FS0/SD
FS1/SEN
A
79–0
B
79–0
CLKB
CSB
ENB
BE/FWFT
SIZE1B
SIZE2B
EF/OR
AE
Rea
d
Dat
a
P
a
th
Lo
gi
c
80
80
Reset
Logic
SIZE1A
SIZE2A
W
ri
te Dat
a
P
a
th
Logi
c
RT/SPM
JTAG Controller
TDI
TCK
TMS
TRST
TDO
OE
Read
Pointer
Pointer
Write
Memory
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
5
Functional Description
The CY7C480XV25 family of FIFOs is comprised of
high-speed, low-power, CMOS Synchronous (clocked) FIFO
memories, meaning both independent ports employ a syn-
chronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of the clock on either port by the
enable signal. The clocks for each port are independent of one
another and can be asynchronous or coincident. The enable
for each port is arranged to provide a simple unidirectional
interface between microprocessors and/or buses with syn-
chronous control.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big Endian or Little Endian byte arrange-
ment, selects the CY standard or First-Word Fall-Through
(FWFT) mode, and determines the configuration of the pro-
grammable flags. The flags can be programmed either in serial
mode or in parallel mode. The FIFO also comes with three
possible default flag offset settings: 8, 16, or 64.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: CY Stan-
dard Mode or First-Word Fall-Through Mode (FWFT). In the
CY Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other subsequent words
residing in memory). In the FWFT Mode, the first word written
to an empty FIFO appears automatically on the outputs, and
no read operation is required. Nevertheless, accessing subse-
quent words does necessitate formal read request. FWFT
mode is primarily used for cascading multiple FIFOs.
The FIFO has an EF/OR flag on port B and FF/IR flag on Port
A. The EF and FF functions are selected in the CY Standard
Mode. EF indicates whether or not the FIFO memory is empty.
FF shows whether or not the memory is full. The IR and OR
functions are selected in the First-Word Fall-Through mode. IR
indicates whether or not the FIFO has memory locations avail-
able. OR shows whether the FIFO has data available for read-
ing or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
FF/IR and AF flags are synchronized to port A clock that writes
data into its array. EF/OR and AE flags are synchronized to
Port B clock that reads data from its array. Programmable off-
sets for AE and AF are loaded in parallel via Port A or in serial
via the SD input. The Serial Programming Mode pin (SPM)
makes this selection. Three default offsets setting are also pro-
vided. The AE threshold can be set at 8, 16, or 64 locations
from the empty boundary and AF threshold can be set at 8, 16,
or 64 locations from the full boundary. All these choices are
made using the FS0 and FS1 inputs during Master Reset.
The CY7C480XV25 FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 85°C indus-
trial.
Selection Guide
CY7C480XV25-200
CY7C480XV25-166
Maximum Frequency (MHz)
200
166
Maximum Access Time (ns)
3.3
3.7
Minimum Cycle Time (ns)
5
6
Minimum Data or Enable Set-Up (ns)
0.9
0.9
Minimum Data or Enable Hold (ns)
0.6
0.6
Maximum Flag Delay (ns)
3.3
3.7
CY7C4808V25
CY7C4806V25
CY7C4804V25
Density
64K x 80
16K x 80
4K x 80
Package
288 FBGA
288 FBGA
288 FBGA
