3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
PRELIMINARY
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 29, 1999
1
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K x 16 organization (CY7C024AV/025AV/026AV)
• 4/8K x 18 organization (CY7C0241AV/0251AV)
• 16K x 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15
[1]
/20/25 ns
• Low operating power
— Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
µ
A (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Master/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
Notes:
1.
Call for availability.
2.
I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
3.
I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
4.
A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
5.
BUSY is an output in master mode and an input in slave mode.
R/W
L
OE
L
I/O
8/9L
–I/O
15/17L
I/O
Control
Address
Decode
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
I/O
0L
–I/O
7/8L
R/W
R
OE
R
I/O
8/9L
–I/O
15/17R
CE
R
UB
R
LB
R
I/O
0L
–I/O
7/8R
UB
L
LB
L
Logic Block Diagram
A
0L
–A
11/1213L
True Dual-Ported
RAM Array
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode
A
0R
–A
11/12/13R
[2]
[2]
[3]
[3]
[5]
[5]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14
12/13/14
[4]
[4]
[4]
[4]
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
2
PRELIMINARY
Functional Description
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV /
036AV are low-power CMOS 4K, 8K, and 16K x16/18 dual-
port static RAMs. Various arbitration schemes are included on
the devices to handle situations when multiple processors ac-
cess the same piece of data. Two ports are provided, permit-
ting independent, asynchronous access for reads and writes
to any location in memory. The devices can be utilized as stan-
dalone 16/18-bit dual-port static RAMs or multiple devices can
be combined in order to function as a 32/36-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 32/36-bit or wider memory applications without the
need for separate master and slave devices or additional dis-
crete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-
port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are available in 100-pin Thin Quad Plastic Flatpacks
(TQFP).
Pin Configurations
Notes:
6.
A
12L
on the CY7C025AV.
7.
A
12R
on the CY7C025AV.
Top View
100-Pin TQFP
100 99
97
98
96
2
3
1
42
41
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28
30
29
31 32
35
34
36 37 38
33
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88
86
87
85
93 92
84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
15L
V
CC
GND
I/O
1R
I/O
2R
V
CC
90
91
A
3L
M/S
BUSY
R
I/O
14L
GND
I/O
12L
I/O
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GN
D
I/O
1L
I/O
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11
L
A
10
L
A
9L
A
8L
A
7L
A
6L
I/O
0R
I/O
7R
I/O
8R
I/O
9R
I/O
10
R
I/O
11
R
I/O
12
R
I/O
13
R
I/O
14
R
GN
D
I/O
15
R
Œ
R
R/W
R
GN
D
SE
M
R
CE
R
UB
R
LB
R
NC
A
11
R
A
10
R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C024AV (4K x 16)
R/
W
L
[6
]
[7
]
CY7C025AV (8K x 16)
