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Desktop/Notebook Frequency Generator

W48S87-72

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 4, 2000 rev. *A

Features

• Maximized EMI suppression using Cypress’s Spread

Spectrum technology

• ±0.5% Spread Spectrum clocking

• Equivalent to the W48S67-72 with Spread Spectrum for

Tilamook, MMO, and Deschutes processors

• Generates system clocks for CPU, IOAPIC, SDRAM,

PCI, USB plus 14.318-MHz (REF0:1)

• Serial data interface (SDATA, SCLOCK inputs) provides

additional CPU/PCI clock frequency selections, individ-

ual output clock disabling and other functions

• MODE input pin selects optional power management

input control pins (reconfigures pins 26 and 27)

• Two fixed outputs separately selectable as 24-MHz or

48-MHz (default = 48-MHz)

• V

DDQ3

= 3.3V±5%, V

DDQ2

= 2.5V±5%

• Uses external 14.318-MHz crystal

• Available in 48-pin SSOP (300 mils)

• 10

Ω

CPU output impedance

Note:

Additional frequency selections provided by serial data interface; refer to Table 5 on page 8.

Table 1. Pin Selectable Frequency

[1]

60/66_SEL

CPU, SDRAM

Clocks (MHz)

PCI Clocks

(MHz)

66.8

33.4

Block Diagram

Pin Configuration

VDDQ3

REF0

VDDQ2

IOAPIC

CPU0

CPU1

CPU2

CPU3

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM7

PCI_F

PCI0

XTAL

PLL Ref Freq

PLL 1

60/66_SEL

MODE

REF1

VDDQ3

Stop

Output

Control

Stop

Output

Control

PCI1

PWR_DWN#

Power

Down

Control

PCI2

PCI3

PCI4

PCI5

48/24MHZ

PLL2

÷2

OSC

I/O

Control

VDDQ2

CPU_STOP#

REF1

REF0

GND

MODE

VDDQ3

PCI_F

PCI0

GND

PCI1

PCI2

PCI3

PCI4

VDDQ3

PCI5

GND

60/66_SEL

SDATA

SCLOCK

VDDQ3

48/24MHZ

GND

87-

VDDQ3

CPU2.5#

VDDQ2

IOAPIC

PWR_DWN#

GND

CPU0

CPU1

VDDQ2

CPU2

CPU3

GND

SDRAM0

SDRAM1

VDDQ3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDDQ3

SDRAM6/CPU_STOP#

SDRAM7/PCI_STOP#

VDDQ3

W48S87-72

Pin Definitions

Pin Name

Pin

No.

Pin

Type

Pin Description

CPU0:3

42, 41, 39,

CPU Outputs 0 through 3: These four CPU outputs are controlled by the

CPU_STOP# control pin. Output voltage swing is controlled by voltage applied

to VDDQ2.

PCI0:5

9, 11, 12,

13, 14, 16

PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the

PCI_STOP# control pin. Output voltage swing is controlled by voltage applied

to VDDQ3.

PCI_F

Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled

by the PCI_STOP# control pin. Output voltage swing is controlled by voltage

applied to VDDQ3.

SDRAM0:5

36, 35, 33,

32, 30, 29

SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run

synchronous to the CPU clock outputs. Output voltage swing is controlled by

voltage applied to VDDQ3.

SDRAM6/

CPU_STOP#

I/O

SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has

dual functions, selectable by the MODE input pin. When MODE = 0, this pin

becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM

clock output 6.

Regarding use as a CPU_STOP# input: When brought LOW, clock outputs

CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock

latency). When brought HIGH, clock outputs CPU0:3 are started beginning with

a full clock cycle (2–3 CPU clock latency).

Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage

applied to VDDQ3.

SDRAM7/

PCI_STOP#

I/O

SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has

dual functions, selectable by the MODE input pin. When MODE = 0, this pin

becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM

clock output 7.

PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW

after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5

are started beginning with a full clock cycle. Clock latency provides one PCI_F

rising edge of PCI clock following PCI_STOP# state change.

Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage

applied to VDDQ3.

IOAPIC

I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output

voltage swing is controlled by VDDQ2.

48/24MHz

22, 23

48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following

device power-up. Either or both can be changed to 24 MHz through use of the

serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled

by voltage applied to VDDQ3

REF0:1

2, 1

Fixed 14.318-MHz Outputs 0 through 1: Used for various system applica-

tions. Output voltage swing is controlled by voltage applied to VDDQ3. REF0

is stronger than REF1 and should be used for driving ISA slots.

CPU_2.5#

Set to logic 0 for V

DDQ2

= 2.5V (0 to 2.5V CPU output swing).

60/66_SEL

60- or 66-MHz Input Selection: Selects power-up default CPU clock frequency

as shown in Table 1 on page 1 (also determines SDRAM and PCI clock fre-

quency selections). Can be used to change CPU clock frequency while device

is in operation if serial data port bits 0–2 of Byte 7 are logic 1 (default power-

up condition).

Crystal Connection or External Reference Frequency Input: This pin has

dual functions. It can be used as an external 14.318-MHz crystal connection

or as an external reference frequency input.

Crystal Connection: An input connection for an external 14.318-MHz crystal.

If using an external reference, this pin must be left unconnected.

W48S87-72

PWR_DWN#

Power-Down Control: When this input is LOW, the device goes into a low-

power standby condition. All outputs are actively held LOW while in power-

down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing

a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU,

SDRAM, and PCI outputs start with a full clock cycle at full operating frequency

(3 ms maximum latency).

MODE

Mode Control: This input selects the function of device pin 26

(SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to descrip-

tion for those pins.

SDATA

I/O

Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

SCLOCK

Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

VDDQ3

7, 15, 21, 25

28, 34, 48

Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output

buffers. Connected to 3.3V supply.

VDDQ2

46, 40

Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Con-

nected to 2.5V supply.

GND

3, 10, 17,

24, 31, 37,

Ground Connection: Connect all ground pins to the common system ground

plane.

Pin Definitions

(continued)

Pin Name

Pin

No.

Pin

Type

Pin Description

W48S87-72

Spread Spectrum Generator

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in Figure 1.

As depicted in Figure 1, a harmonic of a modulated clock has

a much lower amplitude than that of an unmodulated signal.

The reduction in amplitude is dependent on the harmonic num-

ber and the frequency deviation or spread. The equation for

the reduction is

dB = 6.5 + 9*log

(P) + 9*log

(F)

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 2. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is ±0.5% of the center frequen-

cy. Figure 2 details the Cypress spreading pattern. Cypress

does offer options with more spread and greater EMI reduc-

tion. Contact your local Sales representative for details on

these devices.

Spread Spectrum clocking is activated or deactivated by se-

lecting the appropriate values for bits 1–0 in data byte 0 of the

C data stream. Refer to Table 4 for more details.

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Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

Figure 2. Typical Modulation Profile

MAX (+.0.5%)

MIN. (–0.5%)

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

FREQUENCY

W48S87-72

Serial Data Interface

The W48S87-72 features a two-pin, serial data interface that

can be used to configure internal register settings that control

particular device functions. Upon power-up, the W48S87-72

initializes with default register settings, therefore the use of this

serial data interface is optional. The serial interface is write-

only (to the clock chip) and is the dedicated function of device

pins SDATA and SCLOCK. In motherboard applications,

SDATA and SCLOCK are typically driven by two logic outputs

of the chipset. Clock device register changes are normally

made upon system initialization, if any are required. The inter-

face can also be used during system operation for power man-

agement functions. Table 2 summarizes the control functions

of the serial data interface.

Operation

Data is written to the W48S87-72 in ten bytes of eight bits

each. Bytes are written in the order shown in Table 3.

Table 2. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled. Dis-

abled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI

and system power. Examples are clock out-

puts to unused SDRAM DIMM socket or PCI

slot.

48-/24-MHz Clock Output

Frequency Selection

48-/24-MHz clock outputs can be set to 48 MHz or

24 MHz.

Provides flexibility in Super I/O and USB de-

vice selection.

CPU Clock Frequency

Selection

Provides CPU/PCI frequency selections beyond the

60- and 66.6-MHz selections that are provided by

the SEL60/66 input pin. Frequency is changed in a

smooth and controlled fashion.

For alternate CPU devices, and power man-

agement options. Smooth frequency transi-

tion allows CPU frequency change under nor-

mal system operation.

Output Three-state

Puts all clock outputs into a high-impedance state.

Production PCB testing.

Test Mode

All clock outputs toggle in relation with X1 input,

internal PLL is bypassed. Refer to Table 4.

Production PCB testing.

(Reserved)

Reserved function for future device revision or pro-

duction device testing.

No user application. Register bit must be writ-

ten as 0.

Table 3. Byte Writing Sequence

Byte Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for

internal register configuration. Since other devices may exist on the

same common serial data bus, it is necessary to have a specific slave

address for each potential receiver. The slave receiver address for the

W48S87-72 is 11010010. Register setting will not be made if the Slave

Address is not correct (or is for an alternate slave receiver).

Command

Code

Don’t Care

Unused by the W48S87-72, therefore bit values are ignored (don’t care).

This byte must be included in the data write sequence to maintain proper

byte allocation. The Command Code Byte is part of the standard serial

communication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.

Byte Count

Don’t Care

Unused by the W48S87-72, therefore bit values are ignored (don’t care).

This byte must be included in the data write sequence to maintain proper

byte allocation. The Byte Count Byte is part of the standard serial com-

munication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.

Data Byte 0

Refer to Table 4

The data bits in Data Bytes 0–7 set internal W48S87-72 registers that

control device operation. The data bits are only accepted when the Ad-

dress Byte bit sequence is 11010010, as noted above. For description

of bit control functions, refer to Table 4, Data Byte Serial Configuration

Map.

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

W48S87-72

Writing Data Bytes

Each bit in the data bytes control a particular device function

except for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit

7. Table 4 gives the bit formats for registers located in Data

Bytes 0–7.

Table 5 details additional frequency selections that are avail-

able through the serial data interface.

Table 6 details the select functions for Byte 0, bits 1 and 0.

Table 4. Data Bytes 0–7 Serial Configuration Map

Bit(s)

Affected Pin

Control Function

Bit Control

Default

Pin No.

Pin Name

Data Byte 0

(Reserved)

Refer to Table 5

SEL_4

Refer to Table 5

SEL_3

Refer to Table 5

48/24MHZ

48-/24-MHz Clock Output Frequency Selection

24 MHz

48 MHz

48/24MHZ

48-/24-MHz Clock Output Frequency Selection

24 MHz

48 MHz

1–0

Bit 1

Bit 0

Function (See Table 6 for function details)

Normal Operation

Test Mode

Spread Spectrum On

All Outputs Three-stated

Data Byte 1

48/24MHZ

Clock Output Disable

Low

Active

48/24MHZ

Clock Output Disable

Low

Active

(Reserved)

CPU3

Clock Output Disable

Low

Active

CPU2

Clock Output Disable

Low

Active

CPU1

Clock Output Disable

Low

Active

CPU0

Clock Output Disable

Low

Active

Data Byte 2

(Reserved)

PCI_F

Clock Output Disable

Low

Active

PCI5

Clock Output Disable

Low

Active

PCI4

Clock Output Disable

Low

Active

PCI3

Clock Output Disable

Low

Active

PCI2

Clock Output Disable

Low

Active

PCI1

Clock Output Disable

Low

Active

PCI0

Clock Output Disable

Low

Active

Data Byte 3

SDRAM7

Clock Output Disable

Low

Active

SDRAM6

Clock Output Disable

Low

Active

SDRAM5

Clock Output Disable

Low

Active

SDRAM4

Clock Output Disable

Low

Active

SDRAM3

Clock Output Disable

Low

Active

SDRAM2

Clock Output Disable

Low

Active

SDRAM1

Clock Output Disable

Low

Active

SDRAM0

Clock Output Disable

Low

Active

W48S87-72

Data Byte 4

(Reserved)

Data Byte 5

(Reserved)

IOAPIC

Clock Output Disable

Low

Active

(Reserved)

REF1

Clock Output Disable

Low

Active

REF0

Clock Output Disable

Low

Active

Data Byte 6

(Reserved)

Data Byte 7

(Reserved)

SEL_2

Refer to Table 5

SEL_1

Refer to Table 5

SEL_0

Refer to Table 5

Table 4. Data Bytes 0–7 Serial Configuration Map (continued)

Bit(s)

Affected Pin

Control Function

Bit Control

Default

Pin No.

Pin Name

W48S87-72

Notes:

CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5.

In Test Mode, the 48-/24-MHz clock outputs are:

- X1/2 if 48-MHz is selected.

- X1/4 if 24-MHz is selected.

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Date Byte 0

60/66_SEL

(Pin 18)

Date Byte 7

CPU0:3

SDRAM0:7

PCI_F

PCI0:5

Spread

Spectrum%

Bit 5

SEL_4

Bit 4

SEL_3

Bit 2

SEL_2

BIT 1

SEL_1

BIT 0

SEL_0

75.0

CPU/2

±0.5

75.0

±0.5

83.31

±0.5

33.41

CPU/2

±0.5

50.11

CPU/2

±0.5

68.52

CPU/2

±0.5

60.0

CPU/2

±0.5

60.0

CPU/2

±0.5

66.82

CPU/2

±0.5

60.0

CPU/2

±0.5

66.6

CPU/2

–0.5

60.0

CPU/2

±0.5

1</