NM93C46 1024-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus)

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

February 2000

NM93C46

1024-Bit Serial CMOS EEPROM

(MICROWIRE™ Synchronous Bus)

General Description

NM93C46 is a 1024-bit CMOS non-volatile EEPROM organized

as 64 x 16-bit array. This device features MICROWIRE interface

which is a 4-wire serial bus with chipselect (CS), clock (SK), data

input (DI) and data output (DO) signals. This interface is compat-

ible to many of standard Microcontrollers and Microprocessors.

There are 7 instructions implemented on the NM93C46 for various

Read, Write, Erase, and Write Enable/Disable operations. This

device is fabricated using Fairchild Semiconductor floating-gate

CMOS process for high reliability, high endurance and low power

consumption.

“LZ” and “L” versions of NM93C46 offer very low standby current

making them suitable for low power applications. This device is

offered in both SO and TSSOP packages for small space consid-

erations.

Functional Diagram

Features

I Wide V

2.7V - 5.5V

I Typical active current of 200µA

µA standby current typical

µA standby current typical (L)

0.1

µA standby current typical (LZ)

I No Erase instruction required before Write instruction

I Self timed write cycle

I Device status during programming cycles

I 40 year data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

INSTRUCTION

DECODER

CONTROL LOGIC

AND CLOCK

GENERATORS

HIGH VOLTAGE

GENERATOR

AND

PROGRAM

TIMER

INSTRUCTION

ADDRESS

EEPROM ARRAY

READ/WRITE AMPS

DATA IN/OUT REGISTER

16 BITS

DECODER

DATA OUT BUFFER

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N)

8–Pin SO (M8) and 8–Pin TSSOP (MT8)

Top View

Package Number

N08E, M08A and MTC08

Pin Names

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

GND

Ground

No Connect

Power Supply

NOTE:

Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care

should be taken that the voltage applied on these pins does not exceed the V

applied to the device. This will ensure proper operation.

Ordering Information

XXX

Letter Description

Package

8-pin DIP

8-pin SO

MT8

8-pin TSSOP

Temp. Range

None

0 to 70

°C

-40 to +125

°C

-40 to +85

°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 5.5V

2.7V to 5.5V and

µA Standby Current

Blank

Normal Pinout

Rotated Pinout

Density

1024 bits

CMOS

Data protect and sequential

read

Interface

MICROWIRE

Fairchild Memory Prefix

GND

VCC

GND

Normal

Pinout

Rotated

Pinout

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

Absolute Maximum Ratings

(Note 1)

Ambient Storage Temperature

-65

°C to +150°C

All Input or Output Voltages

+6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.)

+300

°C

ESD rating

2000V

Operating Conditions

Ambient Operating Temperature

NM93C46

°C to +70°C

NM93C46E

-40

°C to +85°C

NM93C46V

-40

°C to +125°C

Power Supply (V

)

4.5V to 5.5V

DC and AC Electrical Characteristics

= 4.5V to 5.5V unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

CCA

Operating Current

CS = V

, SK=1.0 MHz

CCS

Standby Current

CS = V

µA

Input Leakage

= 0V to V

±-1

µA

Output Leakage

(Note 2)

Input Low Voltage

-0.1

0.8

Input High Voltage

OL1

Output Low Voltage

= 2.1 mA

0.4

OH1

Output High Voltage

= -400

µA

2.4

OL2

Output Low Voltage

= 10

µA

0.2

OH2

Output High Voltage

= -10

µA

- 0.2

SK Clock Frequency

(Note 3)

MHz

SKH

SK High Time

°C to +70°C

250

-40

°C to +125°C

300

SKL

SK Low Time

250

SKS

SK Setup Time

Minimum CS Low Time

(Note 4)

250

CSS

CS Setup Time

100

DO Hold Time

DIS

DI Setup Time

100

CSH

CS Hold Time

DIH

DI Hold Time

Output Delay

500

CS to Status Valid

500

CS to DO in Hi-Z

CS = V

100

Write Cycle Time

www.fairchildsemi.com

NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

Absolute Maximum Ratings

(Note 1)

Ambient Storage Temperature

-65

°C to +150°C

All Input or Output Voltages

+6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.)

+300

°C

ESD rating

2000V

Operating Conditions

Ambient Operating Temperature

NM93C46L/LZ

°C to +70°C

NM93C46LE/LZE

-40

°C to +85°C

NM93C46LV/LZV

-40

°C to +125°C

Power Supply (V

)

2.7V to 5.5V

DC and AC Electrical Characteristics

= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

CCA

Operating Current

CS = V

, SK=1.0 MHz

CCS

Standby Current

CS = V

µA

LZ (2.7V to 4.5V)

µA

Input Leakage

= 0V to V

±1

µA

Output Leakage

(Note 2)

Input Low Voltage

-0.1

0.15V

Input High Voltage

0.8V

Output Low Voltage

= 10

µA

0.1V

Output High Voltage

= -10

µA

0.9V

SK Clock Frequency

(Note 3)

250

KHz

SKH

SK High Time

µs

SKL

SK Low Time

µs

SKS

SK Setup Time

0.2

µs

Minimum CS Low Time

(Note 4)

µs

CSS

CS Setup Time

0.2

µs

DO Hold Time

DIS

DI Setup Time

0.4

µs

CSH

CS Hold Time

DIH

DI Hold Time

0.4

µs

Output Delay

µs

CS to Status Valid

µs

CS to DO in Hi-Z

CS = V

0.4

µs

Write Cycle Time

Capacitance T

= 25

°C, f = 1 MHz (Note 5)

Symbol

Test

Typ

Max

Units

OUT

Output Capacitance

Input Capacitance

Note 1:

Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of the specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2:

Typical leakage values are in the 20nA range.

Note 3:

The shortest allowable SK clock period = 1/f

(as shown under the f

parameter). Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

in the datasheet. Within this SK period, both t

SKH

and t

SKL

limits must be observed. Therefore, it is not

allowable to set 1/f

= t

SKHminimum

+ t

SKLminimum

for shorter SK cycle time operation.

Note 4:

CS (Chip Select) must be brought low (to V

) for an interval of t

in order to reset all internal

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

Note 5:

This parameter is periodically sampled and not 100% tested.

AC Test Conditions

Range

Input Levels

Timing Level

2.7V

≤ V

≤ 5.5V

0.3V/1.8V

1.0V

0.8V/1.5V

±10µA

(Extended Voltage Levels)

4.5V

≤ V

≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C

= 100 pF)

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

Pin Description

Chip Select (CS)

This is an active high input pin to NM93C46 EEPROM (the device)

and is generated by a master that is controlling the device. A high

level on this pin selects the device and a low level deselects the

device. All serial communications with the device is enabled only

when this pin is held high. However this pin cannot be permanently

tied high, as a rising edge on this signal is required to reset the

internal state-machine to accept a new cycle and a falling edge to

initiate an internal programming after a write cycle. All activity on the

SK, DI and DO pins are ignored while CS is held low.

Serial Clock (SK)

This is an input pin to the device and is generated by the master that

is controlling the device. This is a clock signal that synchronizes the

communication between a master and the device. All input informa-

tion (DI) to the device is latched on the rising edge of this clock input,

while output data (DO) from the device is driven from the rising edge

of this clock input. This pin is gated by CS signal.

Serial Input (DI)

This is an input pin to the device and is generated by the master

that is controlling the device. The master transfers Input informa-

tion (Start bit, Opcode bits, Array addresses and Data) serially via

this pin into the device. This Input information is latched on the

rising edge of the SCK. This pin is gated by CS signal.

Serial Output (DO)

This is an output pin from the device and is used to transfer Output

data via this pin to the controlling master. Output data is serially

shifted out on this pin from the rising edge of the SCK. This pin is

active only when the device is selected.

Microwire Interface

A typical communication on the Microwire bus is made through the

CS, SK, DI and DO signals. To facilitate various operations on the

Memory array, a set of 7 instructions are implemented on NM93C46.

The format of each instruction is listed under Table 1.

Instruction

Each of the 7 instructions is explained under individual instruction

descriptions.

Start bit

This is a 1-bit field and is the first bit that is clocked into the device

when a Microwire cycle starts. This bit has to be “1” for a valid cycle

to begin. Any number of preceding “0” can be clocked into the

device before clocking a “1”.

Opcode

This is a 2-bit field and should immediately follow the start bit.

These two bits (along with 2 MSB of address field) select a

particular instruction to be executed.

Address Field

This is a 6-bit field and should immediately follow the Opcode bits.

In NM93C46, all 6 bits are used for address decoding during

READ, WRITE and ERASE instructions. During all other instruc-

tions, the MSB 2 bits are used to decode instruction (along with

Opcode bits).

Data Field

This is a 16-bit field and should immediately follow the Address

bits. Only the WRITE and WRALL instructions require this field.

D15 (MSB) is clocked first and D0 (LSB) is clocked last (both

during writes as well as reads).

Table 1. Instruction set

Instruction

Start Bit

Opcode Field

Address Field

Data Field

READ

WEN

WRITE

D15-D0

WRALL

D15-D0

WDS

ERASE

ERAL

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

Functional Description

A typical Microwire cycle starts by first selecting the device

(bringing the CS signal high). Once the device is selected, a valid

Start bit (“1”) should be issued to properly recognize the cycle.

Following this, the 2-bit opcode of appropriate instruction should

be issued. After the opcode bits, the 6-bit address information

should be issued. For certain instructions, some of these 6 bits are

don’t care values (can be “0” or “1”), but they should still be issued.

Following the address information, depending on the instruction

(WRITE and WRALL), 16-Bit data is issued. Otherwise, depend-

ing on the instruction (READ), the device starts to drive the output

data on the DO line. Other instructions perform certain control

functions and do not deal with data bits. The Microwire cycle ends

when the CS signal is brought low. However during certain

instructions, falling edge of the CS signal initiates an internal cycle

(Programming), and the device remains busy till the completion of

the internal cycle. Each of the 7 instructions is explained in detail

in the following sections.

1) Read (READ)

READ instruction allows data to be read from a selected location

in the memory array. Input information (Start bit, Opcode and

Address) for this instruction should be issued as listed under

Table1. Upon receiving a valid input information, decoding of the

opcode and the address is made, followed by data transfer from

the selected memory location into a 16-bit serial-out shift register.

This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)

is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit

(logical 0) precedes this 16-bit data output string. Output data

changes are initiated on the rising edge of the SK clock. After

reading the 16-bit data, the CS signal can be brought low to end

the Read cycle. Refer

Read cycle diagram.

2) Write Enable (WEN)

When V

is applied to the part, it “powers up” in the Write Disable

(WDS) state. Therefore, all programming operations must be

preceded by a Write Enable (WEN) instruction. Once a Write

Enable instruction is executed, programming remains enabled

until a Write Disable (WDS) instruction is executed or V

completely removed from the part. Input information (Start bit,

Opcode and Address) for this WEN instruction should be issued

as listed under Table1. The device becomes write-enabled at the

end of this cycle when the CS signal is brought low. Execution of

a READ instruction is independent of WEN instruction. Refer

Write Enable cycle diagram.

3) Write (WRITE)

WRITE instruction allows write operation to a specified location in

the memory with a specified data. This instruction is valid only when

I Device is write-enabled (Refer WEN instruction)

Input information (Start bit, Opcode, Address and Data) for this

WRITE instruction should be issued as listed under Table1. After

inputting the last bit of data (D0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t

time

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

The status of the internal programming cycle can be polled at any

time by bringing the CS signal high again, after t

interval. When

CS signal is high, the DO pin indicates the READY/BUSY status

of the chip. DO = logical 0 indicates that the programming is still

in progress. DO = logical 1 indicates that the programming is

finished and the device is ready for another instruction. It is not

required to provide the SK clock during this status polling. While

the device is busy, it is recommended that no new instruction be

issued. Refer

Write cycle diagram.

It is also recommended to follow this instruction (after the device

becomes READY) with a Write Disable (WDS) instruction to

safeguard data against corruption due to spurious noise, inadvert-

ent writes etc.

4) Write All (WRALL)

Write all (WRALL) instruction is similar to the Write instruction

except that WRALL instruction will simultaneously program all

memory locations with the data pattern specified in the instruction.

This instruction is valid only when

I Device is write-enabled (Refer WEN instruction)

Input information (Start bit, Opcode, Address and Data) for this

WRALL instruction should be issued as listed under Table1. After

inputting the last bit of data (D0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t

time

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. Refer

Write All

cycle diagram.

5) Write Disable (WDS)

Write Disable (WDS) instruction disables all programming opera-

tions and should follow all programming operations. Executing this

instruction after a valid write instruction would protect against

accidental data disturb due to spurious noise, glitches, inadvertent

writes etc. Input information (Start bit, Opcode and Address) for this

WDS instruction should be issued as listed under Table1. The

device becomes write-disabled at the end of this cycle when the CS

signal is brought low.

Execution of a READ instruction is indepen-

dent of WDS instruction. Refer

Write Disable cycle diagram.

6) Erase (ERASE)

The ERASE instruction will program all bits in the specified

location to a logical “1” state. Input information (Start bit, Opcode

and Address) for this WDS instruction should be issued as listed

under Table1. After inputting the last bit of data (A0 bit), CS signal

must be brought low before the next rising edge of the SK clock.

This falling edge of the CS initiates the self-timed programming

cycle. It takes t

time (Refer appropriate DC and AC Electrical

Characteristics table) for the internal programming cycle to finish.

During this time, the device remains busy and is not ready for

another instruction. Status of the internal programming can be

polled as described under WRITE instruction description. While

the device is busy, it is recommended that no new instruction be

issued. Refer

Erase cycle diagram.

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NM93C46 Rev. E

NM93C46 1024-Bit Serial CMOS EEPROM

(MICROWIRE

Synchronous Bus)

7) Erase All (ERAL)

The Erase all instruction will program all locations to a logical “1”

state. Input information (Start bit, Opcode and Address) for this

WDS instruction should be issued as listed under Table1. After

inputting the last bit of data (A0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t

time

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. Refer

Erase

All cycle diagram.

Note:

The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL”

instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The

“ERASE” and “ERASE ALL” instructions are included to maintain compatibility with

earlier technology EEPROMs.Clearing of Ready/Busy status

When programming is in progress, the Data-Out pin will display

the programming status as either BUSY (low) or READY (high)

when CS is brought high (DO output will be tri-stated when CS is

low). To restate, during programming, the CS pin may be brought

high and low any number of times to view the programming status

without affecting the programming operation. Once programming

is completed (Output in READY state), the output is ‘cleared’

(returned to normal tri-state condition) by clocking in a Start Bit.

After the Start Bit is clocked in, the output will return to a tri-stated

condition. When clocked in, this Start Bit can be the first bit in a

command string, or CS can be brought low again to reset all

internal circuits. Refer

Clearing Ready Status diagram.

Related Document

Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-

PROM.