NM27C240

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

NM27C240

4,194,304-Bit (256k x 16) High Performance

CMOS EPROM

General Description

The NM27C240 is a high performance Electrically Programmable

UV erasable ROM (EPROM). It contains 4,194,304 bits config-

ured as 256k x 16 bits. It is offered in both erasable versions for

prototyping and early production applications as well as non-

erasable, plastic packaged versions that are ideal for high volume

and automated assembly applications.

The NM27C240 operates from a single 5V

10% supply in the

read mode.

The NM27C240 is offered in both DIP and surface mount pack-

ages. The DIP package is a 40-pin dual-in-line ceramic with a

quartz window to allow erasing. The surface mount package is a

44-pin PLCC that is offered in OTP.

This EPROM is manufactured using Fairchild’s proprietary AMG™

EPROM technology for an excellent combination of speed and

economy while providing excellent reliability.

Block Diagram

July 1998

Features

High performance CMOS

— 100 ns access time

Fast turn-off for microprocessor compatibility

Simplified upgrade path

— V

and PGM are “Don’t Care” during normal read

operation

Compatible with 27240 and 27C240 EPROMs

JEDEC standard pin configuration

— 40-pin DIP package

— 44-pin PLCC package

Manufacturer’s identification code

Fast programming algorithm

AMG™ is a trademark of WSI, Inc.

Vcc

GND

Vpp

CE/PGM

Output Enable

Chip Enable, and

Program Logic

Decoder

Output

Buffers

4,194,304-Bit

Cell Matrix

A0 - A17

Address

Inputs

Data Outputs O0 - O15

DS011949-1

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

Connection Diagrams

DIP PIN CONFIGURATIONS

Note:

Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C240 pins.

Commercial Temperature Range

C to +70

C) V

= 5V

10%

Parameter/Order Number

Access Time (ns)

NM27C240 Q, V, N 100

100

NM27C240 Q, V, N 120

120

NM27C240 Q, V, N 150

150

Note: Surface mount PLCC package available for commercial and extended

temperature ranges only.

Package types: NM27C240 Q, V, N XXX

Q = Quartz-Windowed Ceramic DIP Package

V = PLCC Package

N = Plastic DIP Package

• All packages conform to JEDEC standard.

• All versions are guaranteed to function in slower applications.

Pin Names

A0–A15

Addresses

CE/PGM

Chip Enable/Program

Output Enable

O0–O15

Outputs

Don’t Care (During Read)

No Connect

Extended Temperature Range

(-40

to +85

C) V

= 5V

10%

Parameter/Order Number

Access Time (ns)

NM27C240 QE, VE, NE 120

120

NM27C240 QE, VE, NE 150

150

PLCC Pin Configuration

27C210 27C220 27C280

A18

CE/PGM

O15

O14

O13

O12

O11

O10

GND

OE/V

XXV

O15

O14

O13

O12

O11

O10

GND

XXV

O15

O14

O13

O12

O11

O10

GND

A17

A16

A15

A14

A13

A12

A11

A10

GND

XX/PGM

A15

A14

A13

A12

A11

A10

GND

PGM

A16

A15

A14

A13

A12

A11

A10

GND

XX/V

CE/PGM

O15

O14

O13

O12

O11

O10

GND

A17

A16

A15

A14

A13

A12

A11

A10

GND

27C280 27C220 27C210

O12

O11

O10

GND

A13

A12

A11

A10

GND

CE/PGM

XX/V

DIP

NM27C240

DS011949-3

DS011949-2

Top View

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

Absolute Maximum Ratings

(Note 1)

Storage Temperature

-65

C to +150

All Input Voltages except A9 with

Respect to Ground (Note 10)

-0.6V to +7V

and A9 with

Respect to Ground

-0.6V to +14V

Supply Voltage with

Respect to Ground

-0.6V to +7V

ESD Protection

>2000V

All Output Voltages with Respect

to Ground (Note 10)

+ 1.0V to GND - 0.6V

Operating Range

Range

Temperature

Tolerance

Commercial

C to +70

+5V

10%

Industrial

-40V

C to +85

+5V

10%

DC Read Characteristics

Over Operating Range with V

= V

Symbol

Parameter

Conditions

Min

Max

Units

Input Low Level

-0.5

0.8

Input High Level

2.0

Output Low Voltage

= 2.1 mA

0.4

Output High Voltage

= -2.5 mA

3.5

SB1

Standby Current (CMOS)

CE = V

0.3V

100

SB2

Standby Current (TTL)

CE = V

Active Current

CE = OE = V

, I/O = 0 mA

f=5 MHz

Supply Current

= V

Input Load Current

= 5.5V or GND

-1

Output Leakage Current

OUT

= 5.5V or GND

-10

AC Read Characteristics

Over Operating Range with V

= V

Symbol

Parameter

100

120

150

Units

Min

Max

Min

Max

Min

Max

ACC

Address to Output Delay

100

120

150

CE to Output Delay

100

120

150

OE to Output Delay

(Note 2)

Output Disable to Output Float

(Note 2)

Output Hold from Addresses CE or

OE , Whichever Occurred First

Capacitance

= +25˚C, f = 1 MHz (Note 2)

Symbol

Parameter

Conditions

Typ

Max

Units

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

AC Test Conditions

Output Load

1 TTL Gate and C

= 100 pF (Note 8)

Input Rise and Fall Times

≤

5 ns

Input Pulse Levels

0.45V to 2.4V

Timing Measurement Reference Level

Inputs

0.8V and 2V

Outputs

0.8V and 2V

AC Waveforms

(Notes 6, 7) (Note 9)

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to t

ACC

–t

after the falling edge of CE without impacting t

ACC

Note 4: The t

and t

compare level is determined as follows:

High to TRI-STATE

, the measured V

OH1

(DC) - 0.10V;

Low to TRI-STATE, the measured V

OL1

(DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1

F ceramic capacitor be used on every device

between V

and GND.

Note 7: The outputs must be restricted to V

+ 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: I

= 1.6 mA, I

= -400

A. C

: 100 pF includes fixture capacitance.

Note 9: V

may be connected to V

except during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

Notes 4, 5

ACC

Note 3

High Z

2.0V

0.8V

Output

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

Adresses

High Z

Addresses Valid

DS011949-4

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

DC Electrical Characteristics

(Notes 11, 12, 13, 14)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Address Setup Time

OES

OE Setup Time

Data Setup Time

2.4

VPS

Setup Time

VCS

Setup Time

Address Hold Time

Data Hold Time

Output Enable to Output Float Delay

CE = V

Program Pulse Width

105

Data Valid from OE

CE = V

100

Supply Current during Programming Pulse

CE = V

, PGM = V

Supply Current

Temperature Ambient

Power Supply Voltage

6.25

6.5

6.75

Programming Supply Voltage

12.5

12.75

13.0

Input Rise, Fall Time

Input Low Voltage

0.0

0.45

Input High Voltage

2.4

4.0

Input Timing Reference Voltage

0.8

2.0

OUT

Output Timing Reference Voltage

0.8

2.0

Programming Waveforms

(Note 13)

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.

Note 12: V

must be applied simultaneously or before V

and removed simultaneously or after V

. The EPROM must not be inserted into or removed from a board with

voltage applied to V

or V

Note 13: The maximum absolute allowable voltage which may be applied to the V

pin during programming is 14V. Care must be taken when switching the V

supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1

F capacitor is required across V

, V

to GND to suppress spurious voltage transients

which may damage the device.

Note 14: During power up the CE/PGM pin must be brought high (

≥

) either coincident with or before power is applied to V

2.0V

0.8V

12.75V

6.25V

2.0V

0.8V

Adresses

Address N

Program

Program Verify

Data In Stable

Add N

Data Out Valid

Add N

Data

OES

High Z

2.0V

0.8V

CE/PGM

2.0V

0.8V

VCS

VPS

DS011949-5

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

Turbo Programming Algorithm Flow Chart

FIGURE 1.

= 6.5V V

= 12.75V

n = 0

ADDRESS = FIRST LOCATION

CHECK ALL BYTES

1ST: V

= V

= 6.0V

2ND: V

= V

= 4.2V

PROGRAM ONE 50

s PULSE

INCREMENT n

ADDRESS = FIRST LOCATION

VERIFY

BYTE

n = 10?

DEVICE

FAILED

LAST

ADDRESS

INCREMENT

ADDRESS

n = 0

PROGRAM ONE

PULSE

INCREMENT

ADDRESS

VERIFY

BYTE

LAST

ADDRESS

PASS

FAIL

YES

PASS

FAIL

YES

DS011949-6

Note:

The standard National Semiconductor algorithm may also be used but it will have longer programming time.

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NM27C240 4,194,304-Bit (256k x 16) High Performance CMOS EPROM

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It

should be noted that all inputs for the six modes are at TTL levels.

The power supplies required are V

and V

. V

power supply

must be at 12.75V during the three programming modes, and must

be at 5V in the other three modes. The V

power supply must be

at 6.5V during the three programming modes, and at 5V in the

other three modes.

Mode Selection

The modes of operation of the NM27C240 are listed in Table 1. A

single 5V power supply is required in the read mode. All inputs are

TTL levels except for V

and A9 for device signature.

TABLE 1. Modes Selection

Pins

Mode

CE/

Outputs

PGM

Read

5.0V

OUT

Output Disable

5.0V

High Z

Standby

5.0V

High Z

Programming

12.75V

6.25V

Program

12.75V

6.25V

OUT

Verify

Program

12.75V

6.25V

High Z

Inhibit

Note 15: X can be V

or V

Read Mode

The EPROM has two control functions, both of which must be

logically active in order to obtain data at the outputs. Chip Enable

(CE) is the power control and should be used for selection. Output

Enable (OE) is the output control and should be used to gate data

to the output pins, independent of the device selection. Assuming

that the addresses are stable, address access time (t

ACC

) is equal

to the delay from CE to output (t

). Data is available at the outputs

after falling edge of OE, assuming that CE has been low and

addresses have been stable for at least t

ACC

- t

Standby Mode

The EPROM standby mode reduces the active power dissipation

by over 99%, from 165 mW to 0.55 mW. The EPROM is placed in

the standby mode by applying a CMOS high signal to the CE input.

When in standby mode, the outputs are in a high impedance state,

independent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL high

signal to the OE input. When in output disable all circuitry is

enabled, except the outputs are in a high impedance state (TRI-

STATE).

Output OR-Tying

Because the EPROM is usually used in larger memory arrays,

Fairchild has provided a 2-line control function that accommo-

dates this use of multiple connections. The 2-line control function

allows for:

1. the lowest possible memory power dissipation, and

2. the complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recommended

that CE be decoded and used as the primary device selecting

function, while OE be made a common connection to all devices

in the array and connected to the READ line from the system

control bus. This assures that all deselected memory devices are

in their low power standby modes and that the output pins are

active only when data is desired from a particular memory device.

Programming