NM27C040

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

NM27C040

4,194,304-Bit (512K x 8) High Performance

CMOS EPROM

General Description

The NM27C040 is a high performance, 4,194,304-bit Electrically

Programmable UV Erasable Read Only Memory. It is organized

as 512K words of 8 bits each. Its pin-compatibility with byte-wide

JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.

The “Don’t Care” feature on V

during read operations allows

memory expansions from 1M to 8 Mbits with no printed circuit

board changes.

The NM27C040 provides microprocessor-based systems exten-

sive storage capacity for large portions of operating system and

application software. Its 120ns access time provides high speed

operation with high-performance CPUs. The NM27C040 offers a

single chip solution for the code storage requirements of 100%

firmware-based equipment. Frequently used software routines

are quickly executed from EPROM storage, greatly enhancing

system utility.

The NM27C040 is manufactured using Fairchild’s advanced

CMOS AMG™ EPROM technology.

Block Diagram

February 1999

Features

High performance CMOS

— 120, 150ns access time*

Simplified upgrade path

—V

is a “Don’t Care” during normal read operation

Manufacturer’s identification code

JEDEC standard pin configuration

— 32-pin PDIP

— 32-pin PLCC

— 32-pin CERDIP

DS010836-1

AMG™ is a trademark of WSI, Inc.

Output Enable,

Chip Enable, and

Program Logic

Y Decoder

X Decoder

. .

. . . . . . .

Output

Buffers

Y Gating

4,194,304-Bit

Cell Matrix

Data Outputs O0 - O7

VCC

GND

VPP

CE/PGM

A0 - A18

Address

Inputs

*Note: New revision meets 70ns. Please check with factory for availability.

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Connection Diagrams

Note:

Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.

Commercial Temperature Range

C to +70

C) V

= 5V

10%

Parameter/Order Number

Access Time (ns)

NM27C040 Q, N, V 120

120

NM27C040 Q, N, V 150

150

Extended Temperature Range

(-40

C to +85

C) V

= 5V

10%

Parameter/Order Number

Access Time (ns)

NM27C040 QE, NE, VE 150

150

Package Types: NM27C040 Q, N,V XXX

Q = Quartz-Windowed Ceramic DIP

N = Plastic DIP

V = PLCC

• All packages conform to the JEDEC standard.

• All versions are guaranteed to function for slower speeds.

Pin Names

A0–A18

Addresses

CE/PGM

Chip Enable/Program

Output Enable

O0–O7

Outputs

Don’t Care (During Read)

XX/V

A16

A15

A12

GND

XX/V

A16

A15

A12

GND

A16

A15

A12

GND

27C020

27C010

XX/V

A16

A15

A12

GND

27C010

27C020

NM27C040

A18

A17

A14

A13

A11

A10

CE/PGM

XX/PGM

A14

A13

A11

A10

XX/PGM

A17

A14

A13

A11

A10

27C080

A18

A17

A14

A13

A11

OE/VPP

A10

CE/PGM

27C080

DS010836-2

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Absolute Maximum Ratings

(Note 1)

Storage Temperature

-65

C to +150

All Input Voltages except A9 with

Respect to Ground

-0.6V to +7V

and A9 with Respect to Ground

-0.6V to +14V

Supply Voltage with

Respect to Ground

-0.6V to +7V

ESD Protection

>2000V

All Output Voltages with

Respect to Ground

+1.0V to GND - 0.6V

Operating Range

Range

Temperature

Tolerance

Commercial

C to +70

+5V

10%

Industrial

-40

C to +85

+5V

10%

Read Operation

DC Electrical Characteristics

Over operating range with V

= V

Symbol

Parameter

Test Conditions

Min

Max

Units

Input Low Level

-0.5

0.8

Input High Level

2.0

Output Low Voltage

= 2.1 mA

0.4

Output High Voltage

= -2.5 mA

3.5

SB1

Standby Current (CMOS)

CE = V

0.3V

100

SB2

Standby Current

CE = V

Active Current

CE = OE = V

f=5 MHz

I/O = 0 mA

Supply Current

= V

Read Voltage

- 0.4

Input Load Current

= 5.5V or GND

-1

Output Leakage Current

OUT

= 5.5V or GND

-10

AC Electrical Characteristics

Over operating range with V

= V

Symbol

Parameter

120

150

Units

Min

Max

Min

Max

ACC

Address to Output Delay

120

150

CE to Output Delay

120

150

OE to Output Delay

Output Disable to

(Note 2)

Output Float

Output Hold from Addresses CE or OE ,

(Note 2)

Whichever Occurred First

Capacitance

= +25

C, f = 1 MHz (Note 2)

Symbol

Parameter

Conditions

Typ

Max

Units

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

AC Test Conditions

Output Load

1 TTL Gate and C

= 100 pF (Note 8)

Input Rise and Fall Times

≤

5 ns

Input Pulse Levels

0.45V to 2.4V

Timing Measurement Reference Level (Note 10)

Inputs

0.8V and 2V

Outputs`

0.8V and 2V

AC Waveforms

(Notes 6, 7, 9)

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to t

ACC

- t

after the falling edge of CE without impacting t

ACC

Note 4: The t

and t

compare level is determined as follows:

High to TRI-STATE

, the measured V

OH1

(DC) - 0.10V;

Low to TRI-STATE, the measured V

OL1

(DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1

F ceramic capacitor be used on every device

between V

and GND.

Note 7: The outputs must be restricted to V

+ 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: I

= 1.6 mA, I

= -400

: 100 pF includes fixture capacitance.

Note 9: V

may be connected to V

except during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

Addresses Valid

Valid Output

Hi-Z

0.8V

ADDRESSES

OUTPUT

tCE

0.8V

(Note 3)

tDF

(Note 4, 5)

tOH

Hi-Z

tOE

ACC

DS010836-4

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Programming Waveform

(Note 13)

Programming Characteristics

(Notes 11, 12, 13, 14)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Address Setup Time

OES

OE Setup Time

Data Setup Time

VPS

Setup Time

VCS

Setup Time

Address Hold Time

Data Hold Time

Output Enable to Output Float Delay

CE/PGM = X

Program Pulse Width

105

Data Valid from OE

CE/PGM = X

100

Supply Current during

CE/PGM = V

Programming Pulse

Supply Current

Temperature Ambient

Power Supply Voltage

6.25

6.5

6.75

Programming Supply Voltage

12.5

12.75

13.0

Input Rise, Fall Time

Input Low Voltage

-0.1

0.0

0.45

Input High Voltage

2.4

4.0

Input Timing Reference Voltage

0.8

2.0

OUT

Output Timing Reference Voltage

0.8

2.0

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.

Note 12: V

must be applied simultaneously or before V

and removed simultaneously or after V

. The EPROM must not be inserted into or removed from a board with

voltage applied to V

or V

Note 13: The maximum absolute allowable voltage which may be applied to the V

pin during programming is 14V. Care must be taken when switching the V

supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1

F capacitor is required across V

, V

to GND to suppress spurious voltage transients

which may damage the device.

Note 14: During power up the CE/PGM pin must be brought high (

≥

) either coincident with or before power is applied to V

Program

Verify

Address N

Data Out Valid

ADD N

Data In Stable

ADD N

Hi-Z

VCS

VPS

OES

0.8V

6.25V

12.75V

0.8V

ADDRESSES

DATA

CE/PGM

DS010836-5

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It

should be noted that all inputs for the six modes are at TTL levels.

The power supplies required are V

and V

. The V

power

supply must be at 12.75V during the three programming modes,

and must be at 5V in the other three modes. The V

power supply

must be at 6.25V during the three programming modes, and at 5V

in the other three modes.

Read Mode

The EPROM has two control functions, both of which must be

logically active in order to obtain data at the outputs. Chip Enable

(CE/PGM) is the power control and should be used for device

selection. Output Enable (OE) is the output control and should be

used to gate data to the output pins, independent of device

selection. Assuming that addresses are stable, address access

time (t

ACC

) is equal to the delay from CE to output (t

). Data is

available at the outputs tOE after the falling edge of OE, assuming

that CE/PGM has been low and addresses have been stable for

at least t

ACC

-t

Standby Mode

The EPROM has a standby mode which reduces the active power

dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM

is placed in the standby mode by applying a CMOS high signal to

the CE/PGM input. When in standby mode, the outputs are in a

high impedance state, independent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL high

signal to the OE input. When in output disable all circuitry is

enabled, except the outputs are in a high impedance state (TRI-

STATE).

Output OR-Typing

Because the EPROM is usually used in larger memory arrays,

Fairchild has provided a 2-line control function that accommo-

dates this use of multiple memory connections. The 2-line control

function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not occur.

To most efficiently use these two control lines, it is recommended

that CE/PGM be decoded and used as the primary device select-

ing function, while OE be made a common connection to all

devices in the array and connected to the READ line from the

system control bus. This assures that all deselected memory

devices are in their low power standby modes and that the output

pins are active only when data is desired from a particular memory

device.

Programming

CAUTION: Exceeding 14V on pin 1 (V

) will damage the EPROM.

Initially, and after each erasure, all bits of the EPROM are in the

“1’s” state. Data is introduced by selectively programming “0’s”

into the desired bit locations. Although only “0’s” will be pro-

grammed, both “1’s” and “0’s” can be presented in the data word.

The only way to change a “0” to a “1” is by ultraviolet light erasure.

The EPROM is in the programming mode when the V

power

supply is at 12.75V and OE is at V

. It is required that at least a

0.1

F capacitor be placed across V

, V

to ground to suppress

spurious voltage transients which may damage the device. The

data to be programmed is applied 8 bits in parallel to the data

output pins. The levels required for the address and data inputs

are TTL.

When the address and data are stable, an active low, TTL program

pulse is applied to the CE/PGM input. A program pulse must be

applied at each address location to be programmed. The EPROM

is programmed with the Turbo Programming Algorithm shown in

Figure 1. Each Address is programmed with a series of 50

pulses until it verifies good, up to a maximum of 10 pulses. Most

memory cells will program with a single 50

s pulse. (The standard

National Semiconductor Algorithm may also be used but it will

have longer programming time.)

The EPROM must not be programmed with a DC signal applied to

the CE/PGM input.

Programming multiple EPROM in parallel with the same data can

be easily accomplished due to the simplicity of the pro-gramming

requirements. Like inputs of the parallel EPROM may be con-

nected together when they are programmed with the same data.

A low level TTL pulse applied to the CE/PGM input programs the

paralleled EPROM.

Program Inhibit

Programming multiple EPROMs in parallel with different data is

also easily accomplished. Except for CE/PGM all like in-puts

(including OE) of the parallel EPROMs may be com-mon. A TTL

low level program pulse applied to an EPROM’s CE/PGM input

with V

at 12.75V will program that EPROM. A TTL high level CE/

PGM input inhibits the other EPROMs from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine

whether they were correctly programmed. The verify may be

performed with V

at 12.75V. V

must be at V

, except during

programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to

prevent unintentional erasure. Covering the window will also

prevent temporary functional failure due to the generation of photo

currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid in

programming. When the device is inserted in an EPROM pro-

grammer socket, the programmer reads the code and then

automatically calls up the specific programming algorithm for the

part. This automatic programming control is only possible with

programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifi-

cally identifies the manufacturer and device type. The code for

NM27C040 is “8F08”, where “8F” designates that it is made by

Fairchild Semiconductor, and “08” designates a 4 Megabit (512K

x 8) part.

The code is accessed by applying 12V

0.5V to address pin A9.

Addresses A1–A8, A10–A18, and all control pins are held at V

Address pin A0 is held at V

for the manufacturer’s code, and held

at V

for the device code. The code is read on the eight data pins,

O0 –O7 . Proper code access is only guaranteed at 25

www.fairchildsemi.com

NM27C040 Rev. C.1

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Functional Description

(Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure

begins to occur when exposed to light with wavelengths shorter

than approximately 4000 Angstroms (Å). It should be noted that

sunlight and certain types of fluorescent lamps have wavelengths

in the 3000Å–4000Å range.

The recommended erasure procedure for the EPROM is expo-

sure to short wave ultraviolet light which has a wavelength of

2537Å. The integrated dose (i.e., UV intensity X exposure time) for

erasure should be minimum of 15W-sec/cm

The EPROM should be placed within 1 inch of the lamp tubes

during erasure. Some lamps have a filter on their tubes which

should be removed before erasure.

An erasure system should be calibrated periodically. The distance

from lamp to device should be maintained at one inch. The erasure

time increase as the square of the distance from the lamp. (If

distance is doubled the erasure time increases by factor of 4.)

Lamps lose intensity as they age. When a lamp is changed, the

distance has changed, or the lamp has aged, the system should

be checked to make certain full erasure is occurring. Incomplete

erasure will cause symptoms that can be misleading. Program-

mers, components, and even system designs have been errone-

ously suspected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful

decoupling of the devices. The supply current, I

, has three

segments that are of interest to the system designer: the standby

current level, the active current level, and the transient current

peaks that are produced by voltage transitions on input pins. The

magnitude of these transient current peaks is dependent of the

output capacitance loading of the device. The associated V

transient voltage peaks can be suppressed by properly selected

decoupling capacitors. It is recommended that at least a 0.1

ceramic capacitor be used on every device between V

and

GND. This should be a high frequency capacitor of low inherent

inductance. In addition, at least a 4.7

F bulk electrolytic capacitor

should be used between V

and GND for each eight devices. The

bulk capacitor should be located near where the power supply is

connected to the array. The purpose of the bulk capacitor is to

overcome the voltage drop caused by the inductive effects of the