1
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
NM27C010
1,048,576-Bit (128K x 8) High Performance
CMOS EPROM
General Description
The NM27C010 is a high performance, 1,048,576-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature during read operations allows memory
expansions from 1M to 8M bits with no printed circuit board
changes.
The NM27C010 can directly replace lower density 28-pin EPROMs
by adding an A16 address line and V
CC
jumper. During the normal
read operation PGM and V
PP
are in a “Don’t Care” state which
allows higher order addresses, such as A17, A18, and A19 to be
connected without affecting the normal read operation. This
allows memory upgrades to 8M bits without hardware changes.
The NM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
The NM27C010 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 70 ns access time provides no-wait-state
operation with high-performance CPUs. The NM27C010 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
Block Diagram
October 1998
The NM27C010 is manufactured using Fairchild’s advanced
CMOS AMG™ EPROM technology.
The NM27C010 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
s
High performance CMOS
— 70 ns access time
s
Fast turn-off for microprocessor compatibility
s
Simplified upgrade path
— V
PP
and PGM are “Don’t Care” during normal read
operation
s
Manufacturers identification code
s
Fast programming
s
JEDEC standard pin configurations
— 32-pin PDIP package
— 32-pin PLCC package
— 32-pin CERDIP package
DS010798-1
© 1998 Fairchild Semiconductor Corporation
NM27C010 ver. 1.1
Output Enable,
Chip Enable, and
Program Logic
Y Decoder
X Decoder
. .
. . . . . . .
Output
Buffers
1,048,576-Bit
Cell Matrix
Data Outputs O
0
- O
7
V
CC
GND
V
PP
OE
PGM
CE
A
0
- A
16
Address
Inputs
2
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Connection Diagrams
DIP PIN CONFIGURATIONS
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C010 pins.
Commercial Temperature Range
(0
°
C to +70
°
C) V
CC
= 5V
±
10%
Parameter/Order Number
Access Time (ns)
NM27C010 Q, V, N 70
70
NM27C010 Q, V, N 90
90
NM27C010 Q, V, N 120
120
NM27C010 Q, V, N 150
150
Extended Temperature Range
(-40
°
C to +85
°
C) V
CC
= 5V
±
10%
Parameter/Order Number
Access Time (ns)
NM27C010 QE, VE, NE 70
70
NM27C010 QE, VE, NE 90
90
NM27C010 QE, VE, NE 120
120
NM27C010 QE, VE, NE 150
150
Package Types: NM27C010 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP package
V = PLCC package
N = Plastic DIP package
• All packages conform to JEDEC standard.
• All versions are guaranteed to function at slower speeds.
Pin Names
A0–A16
Addresses
CE
Chip Enable
OE
Output Enable
O0–O7
Outputs
PGM
Program
XX
Don’t Care (During Read)
PLCC Pin Configuration
Top View
DS010798-10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C040
A
19
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C080
27C020
XX/V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
DIP
NM27C010
V
CC
XX/PGM
XX
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C256
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
27C512
27C020
27C040
V
CC
XX/PGM
A
17
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
27C080
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
27C256
27C512
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
A
12
A
15
A
16
XX/V
PP
V
CC
XX/PGM
XX
O
1
O
2
GND
O
3
O
4
O
5
O
6
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
4 3 2 1 32 31 30
DS010798-3
3
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
-65
°
C to +150
°
C
All Input Voltages Except A9 with
Respect to Ground (Note 10)
-0.6V to +7V
V
PP
and A9 with Respect to Ground
-0.6V to +14V
V
CC
Supply Voltage with
Respect to Ground
-0.6V to +7V
ESD Protection
>2000V
All Output Voltages with
Respect to Ground (Note 10)
V
CC
+ 1.0V to GND - 0.6V
Operating Range
Range
Temperature
V
CC
Tolerance
Commercial
0
°
C to +70
°
C
+5V
±
10%
Extended
-40
°
C to +85
°
C
+5V
±
10%
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
Parameter
Test Conditions
Min
Max
Units
V
IL
Input Low Level
-0.5
0.8
V
V
IH
Input High Level
2.0
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2.5 mA
3.5
V
I
SB1
V
CC
Standby Current
CE = V
CC
±
0.3V
100
µ
A
(CMOS)
I
SB2
V
CC
Standby Current (TTL)
CE = V
IH
1
mA
I
CC
V
CC
Active Current
CE = OE = V
IL
f = 5 MHz
30
mA
I/O = 0 mA
I
PP
V
PP
Supply Current
V
PP
= V
CC
10
µ
A
V
PP
V
PP
Read Voltage
V
CC
- 0.7
V
CC
V
I
LI
Input Load Current
V
IN
= 5.5 or GND
-1
1
µ
A
I
LO
Output Leakage Current
V
OUT
= 5.5V or GND
-10
10
µ
A
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
Parameter
70
90
120
150
Units
Min
Max
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
70
90
120
150
t
CE
CE to Output Delay
70
90
120
150
t
OE
OE to Output Delay
35
40
50
50
t
DF
Output Disable to Output
30
35
35
45
ns
(Note 2)
Float
t
OH
Output Hold from
(Note 2)
Addresses, CE or OE ,
0
0
0
0
Whichever Occurred First
Capacitance
T
A
= +25
°
C, f = 1 MHz (Note 2)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
= 0V
6
15
pF
C
OUT
Output Capacitance
V
OUT
= 0V
10
15
pF
4
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
Input Rise and Fall Times
≤
5 ns
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
0.8V and 2V
Outputs
0.8V and 2V
AC Waveforms
(Note 6), (Note 7), and (Note 9)
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4: The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µ
F ceramic capacitor be used on every device
between V
CC
and GND.
Note 7: The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µ
A.
C
L
: 100 pF includes fixture capacitance.
Note 9: V
PP
may be connected to V
CC
except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics
(Note 11), (Note 12), (Note 13), and (Note 14)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
AS
Address Setup Time
1
µ
s
t
OES
OE Setup Time
1
µ
s
t
CES
CE Setup Time
OE = V
IH
1
µ
s
t
DS
Data Setup Time
1
µ
s
t
VPS
V
PP
Setup Time
1
µ
s
t
VCS
V
CC
Setup Time
1
µ
s
t
AH
Address Hold Time
0
µ
s
t
DH
Data Hold Time
1
µ
s
t
DF
Output Enable to Output Float Delay
CE = V
IL
0
60
ns
t
PW
Program Pulse Width
45
50
105
µ
s
Address Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2V
0.8V
(Note 3)
(Note 3)
t
DF
(Note 4, 5)
(Note 4, 5)
t
OH
Hi-Z
t
OE
t
ACC
t
CF
DS010798-4
5
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Programming Characteristics
(Note 11), (Note 12), (Note 13), and (Note 14) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
OE
Data Valid from OE
CE = V
IL
100
ns
I
PP
V
PP
Supply Current during
CE = V
IL
15
mA
Programming Pulse
PGM = V
IL
I
CC
V
CC
Supply Current
20
mA
T
A
Temperature Ambient
20
25
30
°
C
V
CC
Power Supply Voltage
6.2
6.5
6.75
V
V
PP
Programming Supply Voltage
12.5
12.75
13.0
V
t
FR
Input Rise, Fall Time
5
ns
V
IL
Input Low Voltage
0.0
0.45
V
V
IH
Input High Voltage
2.4
4.0
V
t
IN
Input Timing Reference Voltage
0.8
2.0
V
t
OUT
Output Timing Reference Voltage
0.8
2.0
V
Programming Waveforms
(Note 13)
Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 13: The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µ
F capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the PGM pin must be brought high (
≥
V
IH
) either coincident with or before power is applied to V
PP
.
t
AS
t
AH
Program
Program
Verify
Address N
t
DF
Data Out Valid
ADD N
Data In Stable
ADD N
Hi-Z
t
DS
t
DH
t
VCS
t
VPS
t
CES
t
PW
t
OES
t
OE
2V
0.8V
2V
0.8V
6.25V
12.75V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
DATA
V
CC
CE
PGM
OE
V
PP
DS010798-5
6
www.fairchildsemi.com
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
FIGURE 1.