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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
PRELIMINARY
March 1999
© 1999 Fairchild Semiconductor Corporation
NM25C640
64K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C640 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C640 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
Features
s
2.75 MHz clock rate @ 4.5V to 5.5V
2.1 MHz @ 2.7V to 4.5V
s
65,536 bits organized as 8,192 x 8
s
Multiple chips on the same 3-wire bus with separate chip
select lines
s
Self-timed programming cycle
s
Simultaneous programming of 1 to 32 bytes at a time
s
Status register can be polled during programming to monitor
READY/BUSY
s
Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s
Block write protect feature to protect against accidental
writes
s
Endurance: 1,000,000 data changes
s
Data retention greater than 40 years
s
Packages available: 8-pin DIP or 8-Pin SO
DS500041-1
Instruction
Decoder
Control Logic
and Clock
Generators
High Voltage
Generator
and
Program
Timer
Instruction
Register
Program
Enable
Data In/Out Register
8 Bits
Data Out
Buffer
Non-Volatile
Status Register
Decoder
1 of 8,192
Address
Counter/
Register
EEPROM Array
65,536 Bits
(8,192 x 8)
Read/Write Amps
CS
HOLD
SCK
V
CC
V
SS
V
PP
WP
SI
SO
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N)
and SO Package (M8)
Top View
Pin Names
CS
Chip Select Input
SO
Serial Data Output
WP
Write Protect
V
SS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Suspends Serial Data
V
CC
Power Supply
Ordering Information
NM
25
C
XX
LZ E
XX
Letter
Description
Package
N
8-Pin DIP
M8
8-Pin SO
Temp. Range
None
0 to 70
°
C
V
-40 to +125
°
C
E
-40 to +85
°
C
Voltage Operating Range
Blank
4.5V to 5.5V
L
2.7V to 4.5V
LZ
2.7V to 4.5V and
<1
µ
A Standby Current
Density/Mode
640
64K, mode 0
C
CMOS
Interface
25
SPI
NM
Fairchild Nonvolatile
Memory
CS
SO
WP
V
SS
V
CC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
NM25C640
DS500041-2
3
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5
≤
V
CC
≤
5.5V Specifications
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
-65
°
C to +150
°
C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300
°
C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C640
0
°
C to +70
°
C
NM25C640E
-40
°
C to +85
°
C
NM25C640V
-40
°
C to +125
°
C
Power Supply (V
CC
)
4.5V to 5.5V
DC and AC Electrical Characteristics
4.5V
≤
V
CC
≤
5.5V (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
I
CC
Operating Current
CS = V
IL
3
mA
I
CCSB
Standby Current
CS = V
CC
50
µ
A
I
IL
Input Leakage
V
IN
= 0 to V
CC
-1
+1
µ
A
I
OL
Output Leakage
V
OUT
= GND to V
CC
-1
+1
µ
A
V
IL
CMOS Input Low Voltage
-0.3
V
CC
* 0.3
V
V
IH
CMOS Input High Voltage
V
CC
* 0.7
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -0.8 mA
V
CC
- 0.8
V
f
OP
SCK Frequency
2.75
MHz
t
RI
Input Rise Time
2.0
µ
s
t
FI
Input Fall Time
2.0
µ
s
t
CLH
Clock High Time
(Note 2)
155
ns
t
CLL
Clock Low Time
(Note 2)
155
ns
t
CSH
Min CS High Time
(Note 3)
240
ns
t
CSS
CS Setup Time
176
ns
t
DIS
Data Setup Time
50
ns
t
HDS
HOLD Setup Time
90
ns
t
CSN
CS Hold Time
155
ns
t
DIN
Data Hold Time
50
ns
t
HDN
HOLD Hold Time
90
ns
t
PD
Output Delay
C
L
= 200 pF
135
ns
t
DH
Output Hold Time
0
ns
t
LZ
HOLD to Output Low Z
240
ns
t
DF
Output Disable Time
C
L
= 200 pF
290
ns
t
HZ
HOLD to Output High Z
240
ns
t
WP
Write Cycle Time
1–32 Bytes
10
ms
Capacitance
T
A
= 25
°
C, f = 2.1/1 MHz (Note 4)
Symbol
Test
Typ Max Units
C
OUT
Output Capacitance
3
8
pF
C
IN
Input Capacitance
2
6
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For
example, if the 2.1MHz period = 476ns and t
CLH
= 190ns, t
CLL
must be 286ns.
Note 3: CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Output Load
C
L
= 200 pF
Input Pulse Levels
0.1 * V
CC
– 0.9 * V
CC
Timing Measurement Reference Level
0.3 * V
CC
- 0.7 • V
CC
4
www.fairchildsemi.com
NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 6: The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For
example, if the 2.1MHz period = 476ns and t
CLH
= 190ns, t
CLL
must be 286ns.
Note 7: CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
Low Voltage 2.7V
≤
V
CC
≤
4.5V Specifications
Absolute Maximum Ratings
(Note 5)
Ambient Storage Temperature
-65
°
C to +150
°
C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300
°
C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C640L/LZ
0
°
C to +70
°
C
NM25C640LZ/LZE
-40
°
C to +85
°
C
NM25C640LV
-40
°
C to +125
°
C
Power Supply (V
CC
)
2.7V–4.5V
DC and AC Electrical Characteristics
2.7V
≤
V
CC
≤
4.5V (unless otherwise specified)
25C640L/LE
25C640LV
25C640LZ/LZE
Symbol
Parameter
Part
Conditions
Min.
Max.
Min
Max
Units
I
CC
Operating Current
CS = V
IL
3
3
mA
I
CCSB
Standby Current
L
CS = V
CC
10
10
µ
A
LZ
1
N/A
µ
A
I
IL
Input Leakage
V
IN
= 0 to V
CC
-1
1
-1
1
µ
A
I
OL
Output Leakage
V
OUT
= GND to V
CC
-1
1
-1
1
µ
A
V
IL
Input Low Voltage
-0.3
0.3 * V
CC
-0.3
0.3 * V
CC
V
V
IH
Input High Voltage
0.7 * V
CC
V
CC
+ 0.3
0.7 * V
CC
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 1.6 mA
0.4
0.4
V
V
OH
Output High Voltage
I
OH
= –0.8 mA
V
CC
- 0.8
V
CC
- 0.8
V
f
OP
SCK Frequency
2.1
1.0
MHz
t
RI
Input Rise Time
2.0
2.0
µ
s
t
FI
Input Fall Time
2.0
2.0
µ
s
t
CLH
Clock High Time
(Note 6)
190
410
ns
t
CLL
Clock Low Time
(Note 6)
190
410
ns
t
CSH
Min. CS High Time
(Note 7)
240
500
ns
t
CSS
CS Setup Time
240
500
ns
t
DIS
Data Setup Time
100
100
ns
t
HDS
HOLD Setup Time
90
240
ns
t
CSN
CS Hold Time
240
500
ns
t
DIN
Data Hold Time
100
100
ns
t
HDN
HOLD Hold Time
90
240
ns
t
PD
Output Delay
C
L
= 200 pF
240
500
ns
t
DH
Output Hold Time
0
0
ns
t
LZ
HOLD Output Low Z
100
240
ns
t
DF
Output Disable Time
C
L
= 200 pF
240
500
ns
t
HZ
HOLD to Output Hi Z
100
240
ns
t
WP
Write Cycle Time
1-32 Bytes
15
15
ms
Capacitance
T
A
= 25
°
C, f = 2.1/1 MHz (Note 8)
Symbol
Test
Typ Max Units
C
OUT
Output Capacitance
3
8
pF
C
IN
Input Capacitance
2
6
pF
AC Test Conditions
Output Load
C
L
= 200pF
Input Pulse Levels
0.1 * V
CC
- 0.9 * V
CC
Timing Measurement Reference Level
0.3 * V
CC
- 0.7 * V
CC
5
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
AC Test Conditions
(Continued)
FIGURE 1. Synchronous Data Timing Diagram
FIGURE 3. SPI Serial Interface
SI
SO
SCK
CS
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SPI
CHIP
SELECTION
MASTER MCU
NM25C640
DS500041-3
DS500041-4
SCK
HOLD
SO
tHZ
tHDN
tHDS
tHDN
tHDS
tLZ
DS500041-6
FIGURE 2. Hold Timing
,
,,
CS
SCK
SI
SO
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tCSS
tCSH
tCSN
tDIS
tPD
tDH
tDF
tDIN
tCLH
tCLL
6
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
TABLE 1. Instruction Set
Instruction Instruction
Operation
Name
Opcode
WREN
00000110
Set Write Enable Latch
WRDI
00000100
Reset Write Enable Latch
RDSR
00000101
Read Status Register
WRSR
00000001
Write Status Register
READ
00000011
Read Data from Memory
Array
WRITE
00000010
Write Data to Memory Array
MASTER: The device that generates the serial clock is desig-
nated as the master. The NM25C640 can never function as a
master.
SLAVE: The NM25C640 always operates as a slave as the serial
clock pin is always an input.
TRANSMITTER/RECEIVER: The NM25C640 has separate pins
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit is the first bit transmitted and
received.
CHIP SELECT: The chip is selected when pin CS is low. When the
chip is
not selected, data will not be accepted from pin SI, and the
output pin SO is in high impedance.
SERIAL OP-CODE: The first byte transmitted after the chip is
selected with CS going low contains the op-code that defines the
operation to be performed.
PROTOCOL: When connected to the SPI port of a 68HC11
microcontroller, the NM25C640 accepts a clock phase of 0 and a
clock polarity of 0. The SPI protocol for this device defines the byte
transmitted on the SI and SO data lines for proper chip operation.
See Figure 4.
FIGURE 4. SPI Protocol
…
…
…
CS
SCK
SI
SO
Bit 7 Bit 6
Bit 0
Bit 1
Bit 7
Bit 0
CS
SI
SO
INVALID CODE
DS500041-7
DS500041-5
HOLD: The HOLD pin is used in conjunction with the CS to select
the device. Once the device is selected and a serial sequence is
underway, HOLD may be forced low to suspend further serial
communication with the device without resetting the serial se-
quence. Note that HOLD must be brought low while the SCK pin
is low. The device must remain selected during this sequence. To
resume serial communication HOLD is brought high while the
SCK pin is low. The SO pin is at a high impedance state during
HOLD.
INVALID OP-CODE: After an invalid code is received, no data is
shifted into the NM25C640, and the SO data output pin remains
high impedance until a new CS falling edge reinitializes the serial
communication. See Figure 5 .
FIGURE 5. Invalid Op-Code
Data is clocked in on the positive SCK edge and out on the
negative SCK edge.
7
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
(Continued)
CS
SI
SO
Read
Op-Code
Byte H
Addr. n
Byte L
Addr. n
Data
n
Data
n+1
Data
n+2
Data
n+3
CS
SI
SO
RDSR
Op-Code
SR Data
MSB…LSB
CS
SI
SO
WREN Op-Code
DS500041-8
DS500041-9
DS500041-10
READ SEQUENCE: Reading the memory via the serial SPI link
requires the following sequence. The CS line is pulled low to select
the device. The READ op-code is transmitted on the SI line
followed by the high order address byte (A12–A8), and the low
order address byte (A7–A0). The leading three bits in the high
order address byte will be ignored. After this is done, data on the
SI line becomes don’t care. The data (D7–D0) at the address
specified is then shifted out on the SO line. If only one byte is to
be read, the CS line can be pulled back to the high level. It is
possible to continue the READ sequence as the byte adress is
automatically incremented and data will continue to be shifted out.
When the highest address is reached (1FFF), the address counter
rolls over to lowest address (000) allowing the entire memory to be
read in one continuous READ cycle. See Figure 6.
FIGURE 6. Read Sequence
READ STATUS REGISTER (RDSR) : The Read Status Register
(RDSR) instruction provides access to the status register is used
to interrogate the READY/BUSY and WRITE ENABLE status of
the chip. Two non-volatile status register bits are used to select
one of four levels of BLOCK WRITE PROTECTION. The status
register format is shown in Table 2.
TABLE 2. Status Register Format
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
X
X
X
X
BP1
BP0
WEN
RDY
X = Don't Care.
Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec-
tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 7.
FIGURE 7. Read Status
TABLE 3. Block Write Protection Levels
Level
Status Register Bits
Array
Address
BP1
BP0
Protected
0
0
0
None
1
0
1
1800-1FFF
2
1
0
1000-1FFF
3
1
1
0000–1FFF
WRITE ENABLE (WREN): When V
CC
is applied to the chip, it
“powers up” in the write disable state. Therefore, all programming
modes must be preceded by a WRITE ENABLE (WREN) instruc-
tion. Additionally, the WP must be held high during a write engble
instruction. At the completion of a WRITE or WRSR cycle the
device is automatically returned to the write disable state. Note
that a WRITE DISABLE (WRD) instruction will also return the
device to the write disable state. See Figure 8.
FIGURE 8. Write Enable
WRITE DISABLE (WRDI): To protect against accidental data
disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. See Figure 9.
FIGURE 9. Write Disable
CS
SI
SO
WRDI Op-Code
DS500041-11
8
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NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
(Continued)
WRITE SEQUENCE: To program the device, the WRITE PRO-
TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code is
transmitted on the SI line followed by the high order address byte
(A12-A8) and the low order address byte (A7–A0). The leading