NM24C08U/09U

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

NM24C08U/NM24C09U

8K-Bit Serial EEPROM

2-Wire Bus Interface

General Description,

The NM24C08U/09U devices are 8K (8,192) bit serial interface

CMOS EEPROMs (Electrically Erasable Programmable Read-

Only Memory). These devices fully conform to the Standard I

C™

2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins

to synchronously clock data between the "master" (for example a

microprocessor) and the "slave" (the EEPROM device). In addi-

tion, the serial interface allows a minimal pin count packaging

designed to simplify PC board layout requirements and offers the

designer a variety of low voltage and low power options.

NM24C09U incorporates a hardware "Write Protect" feature, by

which, the upper half of the memory can be disabled against

programming by connecting the WP pin to V

. This section of

memory then effectively becomes a ROM (Read-Only Memory)

and can no longer be programmed as long as WP pin is connected

to V

Fairchild EEPROMs are designed and tested for applications requir-

ing high endurance, high reliability and low power consumption for a

continuously reliable non-volatile solution for all markets.

Block Diagram

August 1999

Functions

C™ compatible interface

8,192 bits organized as 1,024 x 8

Extended 2.7V – 5.5V operating voltage

100 KHz or 400 KHz operation

Self timed programming cycle (6ms typical)

"Programming complete" indicated by ACK polling

NM24C09U: Memory "Upper Block" Write Protect pin

Features

The I

C™ interface allows the smallest I/O pincount of any

EEPROM interface

16 byte page write mode to minimize total write time per byte

Typical 200

A active current (I

CCA

)

Typical 1

A standby current (I

) for "L" devices and 0.1

standby current for "LZ" devices

Endurance: Up to 1,000,000 data changes

Data retention greater than 40 years

H.V. GENERATION

TIMING &CONTROL

E2PROM

ARRAY

YDEC

DATA REGISTER

XDEC

CONTROL

LOGIC

WORD

ADDRESS

COUNTER

SLAVE ADDRESS

COMPARATOR

START

STOP

LOGIC

DIN

R/W

SDA

SCL

VSS

VCC

DOUT

DS800009-1

C™ is a registered trademark of Philips Electronics N.V.

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

Product Specifications

Absolute Maximum Ratings

Ambient Storage Temperature

–65

C to +150

All Input or Output Voltages

with Respect to Ground

6.5V to –0.3V

Lead Temperature

(Soldering, 10 seconds)

+300

ESD Rating

2000V min.

Operating Conditions

Ambient Operating Temperature

NM24C08U/09U

C to +70

NM24C08UE/09UE

-40

C to +85

NM24C08UV/09UV

-40

C to +125

Positive Power Supply

NM24C08U/09U

4.5V to 5.5V

NM24C08UL/09UL

2.7V to 5.5V

NM24C08ULZ/09ULZ

2.7V to 5.5V

Standard V

(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

MinTyp

Max

(Note 1)

CCA

Active Power Supply Current

SCL

= 400 KHz

0.2

1.0

SCL

= 100 KHz

Standby Current

= GND or V

Input Leakage Current

= GND to V

0.1

Output Leakage Current

OUT

= GND to V

0.1

Input Low Voltage

–0.3

x 0.3

Input High Voltage

x 0.7

+ 0.5

Output Low Voltage

= 3 mA

0.4

Low V

(2.7V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

MinTyp

Max

(Note 1)

CCA

Active Power Supply Current

SCL

= 400 KHz

0.2

1.0

SCL

= 100 KHz

Standby Current

= GND

= 2.7V - 4.5V

or V

= 2.7V - 4.5V

0.1

= 4.5V - 5.5V

Input Leakage Current

= GND to V

0.1

Output Leakage Current

OUT

= GND to V

0.1

Input Low Voltage

–0.3

x 0.3

Input High Voltage

x 0.7

+ 0.5

Output Low Voltage

= 3 mA

0.4

Capacitance

= +25

C, f = 100/400 KHz, V

= 5V

(Note 2)

Symbol

Test

Conditions

Max

Units

I/O

Input/Output Capacitance (SDA)

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL)

= 0V

Note 1: Typical values are T

= 25

C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

AC Conditions of Test

Input Pulse Levels

x 0.1 to V

x 0.9

Input Rise and Fall Times

10 ns

Input & Output Timing Levels

x 0.5

Output Load

1 TTL Gate and C

= 100 pF

Read and Write Cycle Limits (Standard and Low V

Range 2.7V - 5.5V)

Symbol

Parameter

100 KHz

400 KHz

Units

MinMax

SCL

SCL Clock Frequency

100

400

KHz

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V

100

Pulse width)

SCL Low to SDA Data Out Valid

0.3

3.5

0.1

0.9

BUF

Time the Bus Must Be Free before

4.7

1.3

a New Transmission Can Start

HD:STA

Start Condition Hold Time

4.0

0.6

LOW

Clock Low Period

4.7

1.5

HIGH

Clock High Period

4.0

0.6

SU:STA

Start Condition Setup Time

4.7

0.6

(for a Repeated Start Condition)

HD:DAT

Data in Hold Time

SU:DAT

Data in Setup Time

250

100

SDA and SCL Rise Time

0.3

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

4.7

0.6

Data Out Hold Time

300

Write Cycle Time - NM24C08U/09U

(Note 3)

- NM24C08U/09UL, NM24C08U/09ULZ

Note 3: The write cycle time (t

) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

NM24C08U/09U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

SDA

SCL

Master

Transmitter/

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Slave

Receiver

Master

Transmitter/

Receiver

VCC

;;

SCL

SDA

OUT

tLOW

tHIGH

tLOW

tAA

tDH

tBUF

tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

tSU:STO

SDA

SCL

NM24C02U/03U

VCC

A0 A1 A2 VSS

NM24C02U/03U

A0 A1 A2 VSS

NM24C04U/05U

A1 A2 VSS

NM24C08U/09U

A2 VSS

VCC

To V

or V

To V

or V

To V

or V

To V

or V

VCC

Bus Timing

System Layout

Typical System Configuration

Note:

Due to open drain configuration of SDA, a bus-level pull-up resistor is called for, (typical value = 4.7k

Ω

)

Example of 16K of Memory on 2-Wire Bus

Note:

The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.

The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.

It is recommended that the total line capacitance be less than 400pF

Device

Address Pins

Memory Size

# of Page

Blocks

NM24C08U/09U

No Connect

ADR

8192 Bits

DS800009-8

DS800009-20

DS800009-9

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

Device Operation Input (A2)

Device address pin A2 is connected to V

or V

to configure

the EEPROM chip address.

Table 1 shows the active pin.

Table 1.

Device

Effects of Addresses

NM24C08U/09U

ADR 2

= 2; 2 x (4 x 2k) = 16K

Background Information (IIC Bus)

As mentioned, the IIC bus allows synchronous bidirectional com-

munication between Transmitter/Receiver using the SCL (clock)

and SDA (Data I/O) lines. All communication must be started with

a valid START condition, concluded with a STOP condition and

acknowledged by the Receiver with an ACKNOWLEDGE condi-

tion.

As shown below, the EEPROMs on the IIC bus may be configured

in any manner required, the total memory addressed can not

exceed 16K (16,384 bits). EEPROM memory address program-

ming is controlled by 2 methods:

• Hardware configuring the A2 pin (Device Address pin) with

pull-up or pull-down to V

or V

. All unused pins must be

grounded (tied to V

• Software addressing the required PAGE BLOCK within the

device memory array (as sent in the Slave Address string).

For devices with densities greater than 16K, a different protocol,

the Extended IIC protocol, is used. Refer to NM24C32U datasheet

(for example) for additional details.

Addressing an EEPROM memory location involves sending a

command string with the following information:

[DEVICE TYPE]–[DEVICE ADDRESS]–[PAGE BLOCK AD-

DRESS]–[BYTE ADDRESS]

DEFINITIONS

BYTE

8 bits (byte) of data

PAGE

16 sequential addresses (one byte

each) that may be programmed

during a 'Page Write' programming

cycle

PAGE BLOCK

2048 (2K) bits organized into 16

pages of addressable memory.

(8 bits) x (16 bytes) x (16 pages)

= 2048 bits

MASTER

Any IIC device CONTROLLING the

transfer of data (such as a

microprocessor)

SLAVE

Device being controlled

(EEPROMs are always considered

Slaves)

TRANSMITTER

Device currently SENDING data on

the bus (may be either a Master or

Slave).

RECEIVER

Device currently RECEIVING data

on the bus (Master or Slave)

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out of the

device. It is an open drain output and may be wire–ORed with any

number of open drain or open collector outputs.

WP Write Protection (NM24C09U Only)

If tied to V

, PROGRAM operations onto the upper half of the

memory will not be executed. READ operations are possible. If

tied to V

, normal operation is enabled, READ/WRITE over the

entire memory is possible.

This feature allows the user to assign the upper half of the memory

as ROM which can be protected against accidental programming.

When write is disabled, slave address and word address will be

acknowledged but data will not be acknowledged.

Device Operation

The NM24C08U/09U supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data onto the bus

as a transmitter and the receiving device as the receiver. The

device controlling the transfer is the master and the device that is

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the NM24C08U/09U will be considered a

slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH are reserved for indicating

start and stop conditions. Refer to

Figure 2 and Figure 3 on next

page.

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

NM24C08U/09U continuously monitors the SDA and SCL lines for

the start condition and will not respond to any command until this

condition has been met.

Stop Condition

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the NM24C08U/09U to place the device

in the standby power mode.

Write Cycle Timing

Acknowledge

Acknowledge is a hardware convention used to indicate success-

ful data transfers. The transmitting device, either master or slave,

will release the bus after transmitting eight bits.

During the ninth clock cycle the receiver will pull the SDA line to

LOW to acknowledge that it received the eight bits of data. Refer

Figure 4.

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

Device Type

Identifier

Device

Address

R/W

(LSB)

NM24C08U/09U

Page

Block Address

DS800009-14

Write Cycle Timing

(Continued)

The NM24C08U/09U device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

both the device and a write operation have been selected, the

NM24C08U/09U will respond with an acknowledge after the

receipt of each subsequent eight bit byte.

In the read mode the NM24C08U/09U slave will transmit eight bits

of data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition is

generated by the master, the slave will continue to transmit data.

If an acknowledge is not detected, the slave will terminate further

data transmissions and await the stop condition to return to the

standby power mode.

Device Addressing

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier (

see Figure 5). This

is fixed as 1010 for all EEPROM devices.

Slave Addresses (Figure 5)

Refer to the following table for Slave Addresses string details:

Device

A0 A1 A2 Page

Page Block

Blocks

Addresses

NM24C08U/09U

00 01 10 11

A: Refers to a hardware configured Device Address pin

P: Refers to an internal PAGE BLOCK memory segment.

All IIC EEPROMs use an internal protocol that defines a PAGE

BLOCK size of 2K bits (for Word addressess 0000 through 1111).

Therefore, address bits A0, A1, or A2 (if designated 'P') are used

to access a PAGE BLOCK in conjunction with the Word address

used to access any individual data byte (Word).

The last bit of the slave address defines whether a write or read

condition is requested by the master. A '1' indicates that a read

operation is to be executed, and a '0' initiates the write mode.

A simple review: After the NM24C08U/09U recognizes the start

condition, the devices interfaced to the IIC bus wait for a slave

address to be transmitted over the SDA line. If the transmitted

slave address matches an address of one of the devices, the

designated slave pulls the line LOW with an acknowledge signal

and awaits further transmissions.

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NM24C08U/09U Rev. B.1

NM24C08U/NM24C09U – 8K-Bit

Serial EEPROM 2-Wire Bus Interface

Write Operations

BYTE WRITE

For a write operation a second address field is required which is

a word address that is comprised of eight bits and provides access

to any one of the 256 bytes in the selected page of memory. Upon

receipt of the byte address the NM24C08U/09U responds with an

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the

NM24C08U/09U begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress the

NM24C08U/09U inputs are disabled, and the device will not

respond to any requests from the master. Refer to

Figure 6 for the

address, acknowledge and data transfer sequence.

PAGE WRITE

The NM24C08U/09U is capable of a sixteen byte page write

operation. It is initiated in the same manner as the byte write

operation; but instead of terminating the write cycle after the first

data byte is transferred, the master can transmit up to fifteen more

bytes. After the receipt of each byte, the NM24C08U/09U will

respond with an acknowledge.

After the receipt of each byte, the internal address counter

increments to the next address and the next SDA data is accepted.

If the master should transmit more than sixteen bytes prior to

generating the stop condition, the address counter will "roll over"

and the previously written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to

Figure 7 for the address, acknowl-

edge, and data transfer sequence.

Bus Activity:

Master

SDA Line

Bus Activity:

NM24C08U/09U

DATA n + 15

DATA n + 1

DATA n

WORD ADDRESS (n)

SLAVE

ADDRESS

DATA

WORD

ADDRESS

SLAVE

ADDRESS

Bus Activity:

Master

SDA Line

Bus Activity:

NM24C08U/09U

DS800009-15

DS800009-16

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s

write operation the NM24C08U/09U initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuing the start condition followed by the slave address for a write

operation. If the NM24C08U/09U is still busy with the write

operation no ACK will be returned. If the NM24C08U/09U has

completed the write operation an ACK will be returned and the

host can then proceed with the next read or write operation.

Write Protection (NM24C09U Only)