NM24C08/09 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

February 2000

NM24C08/09 – 8K-Bit Standard 2-Wire Bus

Interface Serial EEPROM

General Description

The NM24C08/09 devices are 8192 bits of CMOS non-volatile

electrically erasable memory. These devices conform to all speci-

fications in the Standard IIC 2-wire protocol and are designed to

minimize device pin count, and simplify PC board layout require-

ments.

The upper half (upper 4Kbit) of the memory of the NM24C09 can be

write protected by connecting the WP pin to V

. This section of

memory then becomes unalterable unless WP is switched to V

This communications protocol uses CLOCK (SCL) and DATA

I/O (SDA) lines to synchronously clock data between the master

(for example a microprocessor) and the slave EEPROM device(s).

The Standard IIC protocol allows for a maximum of 16K of

EEPROM memory which is supported by the Fairchild family in

2K, 4K, 8K, and 16K devices, allowing the user to configure the

memory as the application requires with any combination of

EEPROMs. In order to implement higher EEPROM memory

densities on the IIC bus, the Extended IIC protocol must be used.

(Refer to the NM24C32 or NM24C65 datasheets for more infor-

mation.)

Fairchild EEPROMs are designed and tested for applications requir-

ing high endurance, high reliability and low power consumption.

Block Diagram

Features

I Extended operating voltage 2.7V – 5.5V

I 400 KHz clock frequency (F) at 2.7V - 5.5V

I 200µA active current typical

µA standby current typical

µA standby current typical (L)

0.1

µA standby current typical (LZ)

I IIC compatible interface

– Provides bi-directional data transfer protocol

I Schmitt trigger inputs

I Sixteen byte page write mode

– Minimizes total write time per byte

I Self timed write cycle

Typical write cycle time of 6ms

I Hardware Write Protect for upper half (NM24C09 only)

I Endurance: 1,000,000 data changes

I Data retention greater than 40 years

I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP

I Available in three temperature ranges

- Commercial: 0

° to +70°C

- Extended (E): -40

° to +85C

- Automotive (V): -40

° to +125°C

H.V. GENERATION

TIMING &CONTROL

E2PROM

ARRAY

YDEC

DATA REGISTER

XDEC

CONTROL

LOGIC

WORD

ADDRESS

COUNTER

SLAVE ADDRESS

COMPARATOR

START

STOP

LOGIC

DIN

R/W

SDA

SCL

VSS

VCC

DOUT

DS500071-1

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

VSS

VCC

SCL

SDA

NM24C08

Connection Diagrams

Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

See Package Number N08E, M08A and MTC08

Pin Names

Device Address Input

Ground

SDA

Serial Data I/O

SCL

Serial Clock Input

No Connection

Power Supply

Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

See Package Number N08E, M08A and MTC08

Pin Names

Device Address Input

Ground

SDA

Serial Data I/O

SCL

Serial Clock input

Write Protect

Power Supply

No Connection

VSS

VCC

SCL

SDA

NM24C09

DS500071-2

DS500071-3

NOTE:

Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care

should be taken that the voltage applied on these pins does not exceed the V

applied to the device. This will ensure proper operation.

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Product Specifications

Absolute Maximum Ratings

Ambient Storage Temperature

–65

°C to +150°C

All Input or Output Voltages

with Respect to Ground

6.5V to –0.3V

Lead Temperature

(Soldering, 10 seconds)

+300

°C

ESD Rating

2000V min.

Operating Conditions

Ambient Operating Temperature

NM24C08/09

°C to +70°C

NM24C08E/09E

-40

°C to +85°C

NM24C08V/09V

-40

°C to +125°C

Positive Power Supply

NM24C08/09

4.5V to 5.5V

NM24C08L/09L

2.7V to 5.5V

NM24C08LZ/09LZ

2.7V to 5.5V

DC Electrical Characteristics (2.7V to 5.5V)

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ

Max

(Note 1)

CCA

Active Power Supply Current

SCL

= 400 KHz

0.2

1.0

SCL

= 100 KHz

Standby Current

= GND

= 2.7V - 5.5V

µA

or V

= 2.7V - 5.5V (L)

µA

= 2.7V - 4.5V (LZ)

0.1

µA

Input Leakage Current

= GND to V

0.1

µA

Output Leakage Current

OUT

= GND to V

0.1

µA

Input Low Voltage

–0.3

x 0.3

Input High Voltage

x 0.7

+ 0.5

Output Low Voltage

= 3 mA

0.4

Capacitance

= +25

°C, f = 100/400 KHz, V

= 5V

(Note 2)

Symbol

Test

Conditions

Max

Units

I/O

Input/Output Capacitance (SDA)

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL)

= 0V

Note 1: Typical values are T

= 25

°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.

Note 2: This parameter is periodically sampled and not 100% tested.

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

AC Test Conditions

Input Pulse Levels

x 0.1 to V

x 0.9

Input Rise and Fall Times

10 ns

Input & Output Timing Levels

x 0.3 to V

x 0.7

Output Load

1 TTL Gate and C

= 100 pF

Bus Timing

DS500071-5

;;

SCL

SDA

OUT

tLOW

tHIGH

tLOW

tAA

tDH

tBUF

tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

tSU:STO

0.9V

0.1V

0.7V

0.3V

Read and Write Cycle Limits (Standard and Low V

Range 2.7V - 5.5V)

Symbol

Parameter

100 KHz

400 KHz

Units

Min

Max

Min

Max

SCL

SCL Clock Frequency

100

400

KHz

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V

100

Pulse width)

SCL Low to SDA Data Out Valid

0.3

3.5

0.1

0.9

µs

BUF

Time the Bus Must Be Free before

4.7

1.3

µs

a New Transmission Can Start

HD:STA

Start Condition Hold Time

4.0

0.6

µs

LOW

Clock Low Period

4.7

1.5

µs

HIGH

Clock High Period

4.0

0.6

µs

SU:STA

Start Condition Setup Time

4.7

0.6

µs

(for a Repeated Start Condition)

HD:DAT

Data in Hold Time

SU:DAT

Data in Setup Time

250

100

SDA and SCL Rise Time

0.3

µs

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

4.7

0.6

µs

Data Out Hold Time

300

Write Cycle Time - NM24C08/09

(Note 3)

- NM24C08/09L, NM24C08/09LZ

Note 3: The write cycle time (t

) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

NM24C08/09 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer

"Write Cycle Timing" diagram.

AC Testing Input/Output Waveforms

DS500071-4

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

SDA

SCL

Master

Transmitter/

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Slave

Receiver

Master

Transmitter/

Receiver

VCC

SDA

SCL

NM24C02/03

VCC

A0 A1 A2 VSS

NM24C02/03

A0 A1 A2 VSS

NM24C04/05

A1 A2 VSS

NM24C08/09

A2 VSS

VCC

Typical System Configuration

Note:

Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k

Ω)

Example of 16K of Memory on 2-Wire Bus

Note:

The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.

The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.

It is recommended that the total line capacitance be less than 400pF

Device

Address Pins Present

Memory Size

# of Page

Blocks

NM24C02/03

Yes

2048 Bits

NM24C04/05

Yes

4096 Bits

NM24C08/09

Yes

8192 Bits

NM24C16/17

16,384 Bits

DS500071-7

DS500071-8

DS500071-6

SDA

SCL

STOP

CONDITION

START

CONDITION

WORD n

8th BIT

ACK

tWR

Write Cycle Timing

Note:

The write cycle time (t

) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Background Information (IIC Bus)

IIC bus allows synchronous bi-directional communication be-

tween a TRANSMITTER and a RECEIVER using a Clock signal

(SCL) and a Data signal (SDA). Additionally there are up to three

Address signals (A2, A1 and A0) which collectively serve as "chip

select signal" to a device (example EEPROM) on the IIC bus.

All communication on the IIC bus must be started with a valid

START condition (by a MASTER), followed by transmittal (by the

MASTER) of byte(s) of information (Address/Data). For every byte

of information received, the addressed RECEIVER provides a valid

ACKNOWLEDGE pulse to further continue the communication

unless the RECEIVER intends to discontinue the communication.

Depending on the direction of transfer (Write or Read), the RE-

CEIVER can be a SLAVE or the MASTER. A typical IIC communi-

cation concludes with a STOP condition (by the MASTER).

Addressing an EEPROM memory location involves sending a

command string with the following information:

[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W

BIT]—{acknowledge pulse}—[ARRAY ADDRESS]

Slave Address

Slave Address is an 8-bit information consisting of a Device type

field (4bits), Device/Page block selection field (3bits) and Read/

Write bit (1bit).

Slave Address Format

Acknowledge

Acknowledge is an active LOW pulse on the SDA line driven by an

addressed receiver to the addressing transmitter to indicate

receipt of 8-bits of data. The receiver provides an ACK pulse for

every 8-bits of data received. This handshake mechanism is done

as follows: After transmitting 8-bits of data, the transmitter re-

leases the SDA line and waits for the ACK pulse. The addressed

receiver, if present, drives the ACK pulse on the SDA line during

the 9th clock and releases the SDA line back (to the transmitter).

Refer

Figure 3.

Array Address

Array address is an 8-bit information containing the address of a

memory location to be selected within a page block of the device.

16K bit Addressing Limitation:

Standard IIC specification limits the maximum size of EEPROM

memory on the bus to 16K bits. This limitation is due to the

addressing protocol implemented which consists of the 8-bit Slave

Address and an additional 8-bit field called Array Address. This

Array Address selects 1 out of 256 locations (2

=256). Since the

data format of IIC specification is 8-bit wide, a total of 256 x 8 =

2048 = 2K bit now becomes addressable by this 8-bit Array

Address. This 2K bit is typically referred as a “Page Block”.

Combining this 8-bit Array Address with the 3-bit Device/Page

address (part of Slave Address) allows a maximum of 8 pages

=8) of memory that can be addressed. Since each page is 2K

bit in size, 8 x 2K bit = 16K bit is the maximum size of memory that

is addressable on the Standard IIC bus. This 16Kb of memory can

be in the form of a single 16Kb EEPROM device or multiple

EEPROMs of varying density (in 2Kb multiples) to a maximum

total of 16Kb. To address the needs of systems that require more

than 16Kb on the IIC bus, a different specification called “Ex-

tended IIC Specification” is used. Please refer to NM24C32xx

Datasheet for more information on Extended IIC Specification.

DEFINITIONS

WORD

8 bits (byte) of data

PAGE

16 sequential byte locations

starting at a 16-byte address

boundary, that may be pro-

grammed during a "page write"

programming cycle

PAGE BLOCK

2048 (2K) bits organized into 16

pages of addressable memory. (8

bits) x (16 bytes) x (16 pages) =

2048 bits

MASTER

Any IIC device CONTROLLING the

transfer of data (such as a

microprocessor)

SLAVE

Device being controlled

(EEPROMs are always considered

Slaves)

TRANSMITTER

Device currently SENDING data on

the bus (may be either a Master or

Slave).

RECEIVER

Device currently RECEIVING data

on the bus (Master or Slave)

Device Type

Identifier

Device/Page Block

Selection

R/W

(LSB)

DS500071-9

Device Type

IIC bus is designed to support a variety of devices such as RAMs,

EPROMs etc., along with EEPROMS. Hence to properly identify

various devices on the IIC bus, a 4-bit “Device Type” identifier

string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC

device on the bus internally compares this 4-bit string to its own

“Device Type” string to ensure proper device selection.

Device/Page Block Selection

When multiple devices of the same type (e.g. multiple EEPROMS)

are present on the IIC bus, then the A2, A1 and A0 address

information bits are also used as part of the Slave Address. Every

IIC device on the bus internally compares this 3-bit string to its own

physical configuration (A2, A1 and A0 pins) to ensure proper

device selection. This comparison is in addition to the “Device

Type” comparison. In addition to selecting an EEPROM, these 3

bits are also used to select a “page block” within the selected

EEPROM. Each page block is 2Kbit (256Bytes) in size. Depend-

ing on the density, an EEPROM can contain from a minimum of 1

to a maximum of 8 page blocks (in multiples of 2) and selection of

a page block within a device is by using A2, A1 and A0 bits.

Read/Write Bit

Last bit of the Slave Address indicates if the intended access is

Read or Write. If the bit is "1," then the access is Read, whereas

if the bit is "0," then the access is Write.

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

EEPROM

Number of

Device Selection Inputs

Address Bits

Density

Page Blocks

Provided

Selecting Page Block

2k bit

None

4k bit

—

8k bit

—

A0 and A1

16k bit

—

A0, A1 and A2

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bi-directional pin used to transfer data into and out of the

device. It is an open drain output and may be wire–ORed with any

number of open drain or open collector outputs.

Write Protect (WP) (NM24C09 Only)

If tied to V

, PROGRAM operations onto the upper half (upper

4Kbit) of the memory will not be executed. READ operations are

possible. If tied to V

, normal operation is enabled, READ/

WRITE over the entire memory is possible.

This feature allows the user to assign the upper half of the memory

as ROM which can be protected against accidental programming.

When write is disabled, slave address and word address will be

acknowledged but data will not be acknowledged.

This pin has an internal pull-down circuit. However, on systems

where write protection is not required it is recommended that this

pin is tied to V

Device Selection Inputs A2, A1 and A0 (as

appropriate)

These inputs collectively serve as “chip select” signal to an

EEPROM when multiple EEPROMs are present on the same IIC

bus. Hence these inputs, if present, should be connected to V

or V

in a unique manner to allow proper selection of an EEPROM

amongst multiple EEPROMs. During a typical addressing se-

quence, every EEPROM on the IIC bus compares the configura-

tion of these inputs to the respective 3 bit “Device/Page block

selection” information (part of slave address) to determine a valid

selection. For e.g. if the 3 bit “Device/Page block selection” is 1-

0-1, then the EEPROM whose “Device Selection inputs” (A2, A1

and A0) are connected to V

-V

respectively, is selected.

Depending on the density, only appropriate number of “Device

Selection inputs” are provided on an EEPROM. For every “Device

selection input” that is not present on the device, the correspond-

ing bit in the “Device/Page block selection” field is used to select

a “Page Block” within the device instead of the device itself.

Following table illustrates the above:

Note that even when just one EEPROM present on the IIC bus,

these pins should be tied to V

or V

to ensure proper termina-

tion.

Device Operation

The NM24C08/09 supports a bi-directional bus oriented protocol.

The protocol defines any device that sends data onto the bus as

a transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device that is

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the NM24C08/09 will be considered a

slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH are reserved for indicating

start and stop conditions. Refer to

Figure 1 and Figure 2 on next

page.

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The NM24C08/

09 continuously monitors the SDA and SCL lines for the start

condition and will not respond to any command until this condition

has been met.

Stop Condition

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the NM24C08/09 to place the device in

the standby power mode, except when a Write operation is being

executed, in which case a second stop condition is required after

period, to place the device in standby mode.

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Acknowledge

The NM24C08/09 device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

both the device and a write operation have been selected, the

NM24C08/09 will respond with an acknowledge after the receipt

of each subsequent eight bit byte.

In the read mode the NM24C08/09 slave will transmit eight bits of

data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected, NM24C08/09 will continue

to transmit data. If an acknowledge is not detected,NM24C08/09

will terminate further data transmissions and await the stop

condition to return to the standby power mode.

Device Addressing

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier. This is fixed as

1010 for all EEPROM devices.

Refer the following table for Slave Addresses string details:

Device

A0 A1 A2 Page

Page Block

Blocks

Addresses

NM24C08/09

00, 01, 10, 11

A: Refers to a hardware configured Device Address pin.

P: Refers to an internal PAGE BLOCK.

All IIC EEPROMs use an internal protocol that defines a PAGE

BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).

Therefore, address bits A0, A1, or A2 (if designated 'P') are used

to access a PAGE BLOCK in conjunction with the Word address

used to access any individual data byte.

The last bit of the slave address defines whether a write or read

condition is requested by the master. A '1' indicates that a read

operation is to be executed, and a '0' initiates the write mode.

A simple review: After the NM24C08/09 recognizes the start

condition, the devices interfaced to the IIC bus wait for a slave

address to be transmitted over the SDA line. If the transmitted

slave address matches an address of one of the devices, the

designated slave pulls the line LOW with an acknowledge signal

and awaits further transmissions.

Device Type

Identifier

Device

Address

R/W

(LSB)

NM24C08/09

Page

Block Address

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NM24C08/09 Rev. G

NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Write Operations

BYTE WRITE

For a write operation a second address field is required which is

a word address that is comprised of eight bits and provides access

to any one of the 256 bytes in the selected page of memory. Upon

receipt of the byte address the NM24C08/09 responds with an

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the NM24C08/

09 begins the internal write cycle to the nonvolatile memory. While

the internal write cycle is in progress the NM24C08/09 inputs are

disabled, and the device will not respond to any requests from the

master for the duration of t

. Refer to

Figure 4 for the address,

acknowledge and data transfer sequence.

PAGE WRITE

To minimize write cycle time, NM24C08/09 offer Page Write

feature, by which, up to a maximum of 16 contiguous bytes

locations can be programmed all at once (instead of 16 individual

byte writes). To facilitate this feature, the memory array is orga-

nized in terms of “Pages.” A Page consists of 16 contiguous byte

locations starting at every 16-Byte address boundary (for ex-

ample, starting at array address 0x00, 0x10, 0x20 etc.). Page

Write operation limits access to byte locations within a page. In

other words a single Page Write operation will not cross over to

locations on another page but will “roll over” to the beginning of the

page whenever end of Page is reached and additional locations

are a continued to be accessed. A Page Write operation can be

initiated to begin at any location within a page (starting address of

the Page Write operation need not be the starting address of a

Page).

Bus Activity:

Master

SDA Line

Bus Activity:

EEPROM

DATA n + 15

DATA n + 1

DATA n

WORD ADDRESS (n)

SLAVE

ADDRESS