© 1999 Fairchild Semiconductor Corporation
DS500169
www.fairchildsemi.com
May 1999
Revised September 1999
GTLP18T
612 18
-Bit
L
V
TTL/
GTLP Uni
vers
a
l
Bus T
ranscei
ver
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down high impedance for live insertion
s
External V
REF
pin for receiver threshold
s
BiCMOS technology for low power dissipation
s
Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s
LVTTL compatible Driver and Control inputs
s
Flow-through architecture optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A-Port source/sink
−
24 mA/
+
24 mA
s
B-Port sink capability +50 mA
s
D-type flip-flop, latch and transparent data paths
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
GTLP18T612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
GTLP18T612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
GTLP18T612
Pin Descriptions
Connection Diagram
Functional Description
The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation
for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB
and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and
the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is
similar except that CEBA, OEBA, LEBA, and CLKBA are used.
Pin Names Description
OEAB
A-to-B Output Enable
(Active LOW) (LVTTL Level)
OEBA
B-to-A Output Enable
(Active LOW) (LVTTL Level)
CEAB
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)
CEBA
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)
LEAB
A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
LEBA
B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
V
REF
GTLP Input Threshold
Reference Voltage
CLKAB
A-to-B Clock (LVTTL Level)
CLKBA
B-to-A Clock (LVTTL Level)
A1–A18
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B1–B18
B-to-A Data Inputs or
A-to-B Open Drain Outputs
3
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GTLP18T
612
Truth Table
(Note 1)
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
Logic Diagram
Inputs
Output
B
Mode
CEAB
OEAB
LEAB
CLKAB
A
X
H
X
X
X
Z
Latched
L
L
L
H or L
X
B
0
(Note 2)
storage
L
L
L
H or L
X
B
0
(Note 3)
of A data
X
L
H
X
L
L
Transparent
X
L
H
X
H
H
L
L
L
↑
L
L
Clocked
L
L
L
↑
H
H
storage
of A data
H
L
L
X
X
B
0
(Note 3)
Clock inhibit
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4
GTLP18T612
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
(Note 6)
Note 4: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.
Note 5: I
O
Absolute Maximum Rating must be observed.
Note 6: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Supply Voltage (V
CC
)
−
0.5V to
+
4.6V
DC Input Voltage (V
I
)
−
0.5V to
+
4.6V
DC Output Voltage (V
O
)
Outputs 3-STATE
−
0.5V to
+
4.6V
Outputs Active (Note 5)
−
0.5V to V
CC
+
0.5V
DC Output Sink Current into
A Port I
OL
48 mA
DC Output Source Current from
A Port I
OH
−
48 mA
DC Output Sink Current into
B Port in the LOW State, I
OL
100 mA
DC Input Diode Current (I
IK
)
V
I
<
0V
−
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
−
50 mA
V
O
>
V
CC
+
50 mA
ESD Performance
>
2000V
Storage Temperature (T
STG
)
−
65
°
C to
+
150
°
C
Supply Voltage V
CC
/V
CCQ
3.15V to 3.45V
Bus Termination Voltage (V
TT
)
GTLP
1.47V to 1.53V
V
REF
0.98V to 1.02V
Input Voltage (V
I
)
on A Port and Control Pins
0.0V to 3.45V
on B Port
0.0V to 3.45V
HIGH Level Output Current (I
OH
)
A Port
−
24 mA
LOW Level Output Current (I
OL
)
A Port
+
24 mA
B Port
+
50 mA
Operating Temperature (T
A
)
−
40
°
C to
+
85
°
C
Symbol
Test Conditions
Min
Typ
Max
Units
(Note 7)
V
IH
B Port
V
REF
+
0.05
V
TT
V
Others
2.0
V
IL
B Port
0.0
V
REF
−
0.05
V
Others
0.8
V
REF
GTLP (Note 8)
1.0
V
GTL
0.8
V
IK
V
CC
=
3.15V
I
I
=
−
18 mA
−
1.2
V
V
OH
A Port
V
CC
, V
CCQ
=
Min to Max (Note 9)
I
OH
=
−
100
µ
A
V
CC
–0.2
V
V
CC
=
3.15V
I
OH
=
−
8 mA
2.4
I
OH
= -24mA
2.0
V
OL
A Port
V
CC
, V
CCQ
=
Min to Max (Note 9)
I
OL
=
100
µ
A
0.2
V
V
CC
=
3.15V
I
OL
=
24mA
0.5
B Port
V
CC
=
3.15V
I
OL
=
40 mA
0.40
V
I
OL
=
50 mA
0.55
I
I
Control Pins
V
CC
=
Min to Max (Note 9)
V
I
=
3.45V or 0V
±
5
µ
A
A Port
V
CC
=
3.45V
V
I
=
0V
−
10
µ
A
V
I
=
3.45
10
B Port
V
CC
=
3.45V
V
I
=
V
CC
5
µ
A
V
I
=
0
−
5
I
OFF
A Port and Control Pins V
CC
=
0
V
I
or V
O
=
0 to 3.45V
30
µ
A
I
I(hold)
A Port
V
CC
=
3.15V
V
I
=
0.8V
75
µ
A
V
I
=
2.0V
−
75
I
OZH
A Port
V
CC
=
3.45V
V
O
=
3.45
10
µ
A
B Port
V
O
=
1.5V
5
I
OZL
A Port
V
CC
=
3.45V
V
O
=
0V
−
10
µ
A
B Port
V
O
=
0.55V
−
5
5
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GTLP18T
612
DC Electrical Characteristics
(Continued)
Note 7: All typical values are at V
CC
=
3.3V, V
CCQ
=
3.3V, and T
A
=
25
°
C.
Note 8: GTLP V
REF
and V
TT
are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In
addition, V
TT
and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50
Ω
, but must
remain within the boundaries of the DC Absolute Maximum ratings. Similarly V
REF
can be adjusted to optimize noise margin.
Note 9: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 10: This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
Symbol
Test Conditions
Min
Typ
Max
Units
(Note 7)
I
CC
A or B Ports
V
CC
=
3.45V
Outputs HIGH
30
40
mA
(V
CC
/V
CCQ
)
I
O
=
0
Outputs LOW
30
40
V
I
=
V
CC
or GND
Outputs Disabled
30
45
∆
I
CC
A Port and
V
CC
=
3.45V,
One Input at 2.7V
0
2
mA
(Note 10)
Control Pins
A or Control Inputs at V
CC
or GND
C
i
Control Pins
V
I
=
V
CC
or 0
6
A Port
V
I
=
V
CC
or 0
7.5
pF
B Port
V
I
=
V
CC
or 0
9.0
Symbol
Test Conditions
Min
Max
Unit
f
CLOCK
Maximum Clock Frequency
0
175
MHz
t
WIDTH
Pulse Duration
LEAB or LEBA HIGH
3.0
ns
CLKAB or CLKBA HIGH or LOW
3.0
t
SU
Setup Time
A before CLKAB
↑
1.1
ns
B before CLKBA
↑
3.0
A before LEAB
1.1
B before LEBA
2.7
CEAB before CLKAB
↑
1.2
CEBA before CLKBA
↑
1.4
t
HOLD
Hold Time
A after CLKAB
↑
0.0
ns
B after CLKBA
↑
0.0
A after LEAB
0.8
B after LEBA
0.0
CEAB after CLKAB
↑
1.0
CEBA after CLKBA
↑
1.9
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6
GTLP18T612
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
C
L
=
30 pF for B Port and C
L
=
50 pF for A Port.
Note 11: All typical values are at V
CC
=
3.3V, and T
A
=
25
°
C.
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature V
REF
=
1.0V (unless otherwise noted).
C
L
=
30 pF for B Port and C
L
=
50 pF for A Port.
Note 12: t
OSHL
/t
OSLH
and t
OST
- Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case V
CC
and temperature and apply to any outputs switching in the same
direction either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
) or in opposite directions both HL and LH (t
OST
). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 13: t
PV
- Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device.
The parameter is specified for a specific worst case V
CC
and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Note 14: Due to the open drain structure on GTLP outputs t
OST
and t
PV(LH)
in the A-to-B direction are not specified. Skew on these paths is dependent on the
V
TT
and R
T
values on the backplane.
Symbol
From
To
Min
Typ
Max
Unit
(Input)
(Output)
(Note 11)
t
PLH
A
B
2.1
4.1
6.3
ns
t
PHL
1.0
2.7
4.4
t
PLH
LEAB
B
2.2
4.2
6.3
ns
t
PHL
1.0
2.4
4.2
t
PLH
CLKAB
B
2.2
4.4
6.5
ns
t
PHL
1.0
2.5
4.4
t
PLH
OEAB
B
2.0
3.8
5.6
ns
t
PHL
1.0
2.6
4.3
t
RISE
Transition time, B outputs (20% to 80%)
3.1
ns
t
FALL
Transition time, B outputs (20% to 80%)
2.1
t
PLH
B
A
1.8
3.8
5.8
ns
t
PHL
1.8
3.8
5.8
t
PLH
LEBA
A
0.3
2.2
4.6
ns
t
PHL
0.4
2.4
4.6
t
PLH
CLKBA
A
0.5
2.4
4.6
ns
t
PHL
0.6
2.6
4.6
t
PZH
, t
PZL
OEBA
A
0.3
2.7
5.2
ns
t
PHZ
, t
PLZ
0.3
2.5
5.2
Symbol
From
(Input)
To
(Output)
Min
Typ
(Note 11)
Max
Unit
t
OSLH
(Note 12)
A
B
0.8
1.0
ns
t
OSHL
(Note 12)
0.3
0.5
ns
t
PV(HL)
(Note 13)(Note 14)
A
B
0.8
ns
t
OSLH
(Note 12)
CLKAB
B
0.9
1.0
ns
t
OSHL
(Note 12)
0.3
0.5
ns
t
PV(HL)
(Note 13)(Note 14)
CLKAB
B
0.8
ns
t
OSLH
(Note 12)
B
A
0.7
1.0
ns
t
OSHL
(Note 12)
0.6
1.0
ns
t
OST
(Note 12)
B
A
0.7
1.1
ns
t
PV
(Note 13)
B
A
1.5
ns
t
OSLH
(Note 12)
CLKAB
A
0.5
1.0
ns
t
OSHL
(Note 12)
0.6
1.0
ns
t
OST
(Note 12)
CLKAB
A
1.1
1.2
ns
t
PV
(Note 13)
CLKAB
A
1.5
ns
7
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GTLP18T
612
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
Note A: C
L
includes probes and Jig capacitance.
Test Circuit for B Outputs
Note B: For B Port, C
L
=
30 pF is used for worst case.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.
Input and Measure Conditions
All input pulses have the following characteristics: Frequency
=
10MHz, t
RISE
=
t
FALL
=
2 ns (10% to 90%), Z
O
=
50
Ω
.
The outputs are measured one at a time with one transition per measurement.
Test
S
t
PLH
/t
PHL
Open
t
PLZ
/t
PZL
6V
t
PHZ
/t
PZH
GND
A or LVTTL
Pins
B or GTLP
Pins
V
inHIGH
3.0