© 2000 Fairchild Semiconductor Corporation
DS500037
www.fairchildsemi.com
July 1997
Revised August 2000
FST1
621
1 24-Bi
t Bus
Swi
tch
FST16211
24-Bit Bus Switch
General Description
The Fairchild Switch FST16211 provides 24-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 12-bit or 24-bit bus switch.
When OE
1
is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE
2
is LOW, Port 2A is connected
to Port 2B. When OE
1/2
is HIGH, a high impedance state
exists between the A and B Ports.
Features
s
4
Ω
switch connection between two ports
s
Minimal propagation delay through the switch
s
Low l
CC
s
Zero bounce in flow-through mode
s
Control inputs compatible with TTL level
s
Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.
Logic Diagram
Order Number
Package Number
Package Description
FST16211GX
(Note 1)
BGA54A
Preliminary
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
[TAPE and REEL]
FST16211MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16211MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
FST1621
1
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
TOP VIEW
Pin Descriptions
FBGA Pin Assignments
Truth Table
Pin Name
Description
OE
1
, OE
2
Bus Switch Enables
1A, 2A
Bus A
1B, 2B
Bus B
1
2
3
4
5
6
A
1A
2
1A
1
NC
OE
2
1B
1
1B
2
B
1A
4
1A
3
1A
7
OE
1
1B
3
1B
4
C
1A
6
1A
5
GND
1B
7
1B
5
1B
6
D
1A
10
1A
9
1A
8
1B
8
1B
9
1B
10
E
1A
12
1A
11
2A
1
2B
1
1B
11
1B
12
F
2A
4
2A
3
2A
2
2B
2
2B
3
2B
4
G
2A
6
2A
5
V
CC
GND
2B
5
2B
6
H
2A
8
2A
7
2A
11
2B
11
2B
7
2B
8
J
2A
10
2A
9
2A
12
2B
12
2B
9
2B
10
Inputs
Inputs/Outputs
OE
1
OE
2
1A, 1B
2A, 2B
L
L
1A
=
1B
2A
=
2B
L
H
1A
=
1B
Z
H
L
Z
2A
=
2B
H
H
Z
Z
3
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FST1
621
1
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 5)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3: V
S
is the voltage observed/applied at either A or B Ports across the
switch.
Note 4: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 5: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 6: Typical values are at V
CC
=
5.0V and T
A
=
+
25
°
C
Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (V
CC
)
−
0.5V to
+
7.0V
DC Switch Voltage (V
S
) (Note 3)
−
0.5V to
+
7.0V
DC Input Voltage (V
IN
) (Note 4)
−
0.5V to
+
7.0V
DC Input Diode Current (l
IK
) V
IN
<
0V
−
50mA
DC Output (I
OUT
) Sink Current
128mA
DC V
CC
/GND Current (I
CC
/I
GND
)
+
/
−
100mA
Storage Temperature Range (T
STG
)
−
65
°
C to
+
150
°
C
Power Supply Operating (V
CC)
4.0V to 5.5V
Input Voltage (V
IN
)
0V to 5.5V
Output Voltage (V
OUT
)
0V to 5.5V
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
0nS/V to 5nS/V
Switch I/O
0nS/V to DC
Free Air Operating Temperature (T
A
)
-40
°
C to
+
85
°
C
Symbol
Parameter
V
CC
(V)
T
A
=
−
40
°
C to
+
85
°
C
Units
Conditions
Min
Typ
(Note 6)
Max
V
IK
Clamp Diode Voltage
4.5
−
1.2
V
I
IN
=
−
18mA
V
IH
HIGH Level Input Voltage
4.0–5.5
2.0
V
V
IL
LOW Level Input Voltage
4.0–5.5
0.8
V
I
I
Input Leakage Current
5.5
±
1.0
µ
A
0
≤
V
IN
≤
5.5V
0
10
µ
A
V
IN
=
5.5V
I
OZ
OFF-STATE Leakage Current
5.5
±
1.0
µ
A
0
≤
A, B
≤
V
CC
R
ON
Switch On Resistance
4.5
4
7
Ω
V
IN
=
0V, I
IN
=
64mA
(Note 7)
4.5
4
7
Ω
V
IN
=
0V, I
IN
=
30mA
4.5
8
12
Ω
V
IN
=
2.4V, I
IN
=
15mA
4.0
11
20
Ω
V
IN
=
2.4V, I
IN
=
15mA
I
CC
Quiescent Supply Current
5.5
3
µ
A
V
IN
=
V
CC
or GND, I
OUT
=
0
∆
I
CC
Increase in I
CC
per Input
5.5
2.5
mA
One input at 3.4V
Other inputs at V
CC
or GND
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4
FST1621
1
AC Electrical Characteristics
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 9)
Note 9: T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50
Ω
source terminated in 50
Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol
Parameter
T
A
=
−
40
°
C to
+
85
°
C,
Units
Conditions
Figure
No.
C
L
=
50pF, RU
=
RD
=
500
Ω
V
CC
=
4.5 – 5.5V
V
CC
=
4.0V
Min
Max
Min
Max
t
PHL
,t
PLH
Prop Delay Bus to Bus (Note 8)
0.25
0.25
ns
V
I
=
OPEN
Figures
1, 2
t
PZH
, t
PZL
Output Enable Time
1.5
6.0
6.5
ns
V
I
=
7V for t
PZL
Figures
1, 2
V
I
=
OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time
1.5
7.0
7.2
ns
V
I
=
7V for t
PLZ
Figures
1, 2
V
I
=
OPEN for t
PHZ
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Control Pin Input Capacitance
3
pF
V
CC
=
5.0V
C
I/O
Input/Output Capacitance
6
pF
V
CC
, OE
=
5.0V
5
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FST1
621
1
Physical Dimensions
inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
Package Number BGA54A
Preliminary
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6
FST1621
1
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
7
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FST1
621
1
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
8
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FST1
621
1 24-Bi
t Bus
Swi
tch
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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