© 2000 Fairchild Semiconductor Corporation
DS006331
www.fairchildsemi.com
October 1986
Revised March 2000
DM74AS874
Dual
4-
Bit
D-
T
y
pe Edge-
T
ri
ggere
d
Fl
ip-
F
lo
p
DM74AS874
Dual 4-Bit D-Type Edge-Triggered Flip-Flop
General Description
These dual 4-bit inverting registers feature totem-pole 3-
STATE outputs designed specifically for driving highly-
capacitive or relatively low-impedance loads. The high-
impedance state and increased high-logic-level drive pro-
vide these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components. They
are particularly attractive for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74AS874 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all
outputs are on the other side.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer-type outputs drive bus lines directly
s
Space saving 300 mil wide package
s
Bus structured pinout
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
Package Description
DM74AS874WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS874NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com
2
DM
74AS874
Function Table
L
=
LOW State
H
=
HIGH State
X
=
Don’t Care
↑
=
Positive Edge Transition
Z
=
High Impedance State
Q
0
=
Previous Condition of Q
Logic Diagram
Inputs
Output
CLR
D
CLK
OC
Q
X
X
X
H
Z
L
X
X
L
L
H
H
↑
L
H
H
L
↑
L
L
H
X
L
L
Q
0
3
www.fairchildsemi.com
DM74AS874
Absolute Maximum Ratings
(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: The (
↑
) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
°
C.
Note 3: The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit current, I
OS
.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
0
°
C to
+
70
°
C
Storage Temperature Range
−
65
°
C to
+
150
°
C
Typical
θ
JA
N Package
47.0
°
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
−
15
mA
I
OL
LOW Level Output Current
48
mA
f
CLK
Clock Frequency
0
80
MHz
t
WCLK
Width of Clock Pulse
HIGH
3
ns
LOW
6
t
WCLR
Width of Clear Pulse
LOW
2
ns
t
SU
Setup Time
Data
4
↑
ns
(Note 2)
Clear Inactive
5
↑
t
H
Data Hold Time (Note 2)
1
↑
ns
T
A
Free Air Operating Temperature
0
70
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
−
18 mA
−
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V, V
IL
=
V
IL
Max, I
OH
=
Max
2.4
3.3
V
Output Voltage
I
OH
=
−
2 mA, V
CC
=
4.5V to 5.5V
V
CC
−
2
V
OL
LOW
Level V
CC
=
4.5V, V
IH
=
2V,
0.35
0.5
V
Output Voltage
I
OL
=
Max
I
I
Input Current at Max Input Voltage V
CC
=
5.5V, V
IH
=
7V
0.1
mA
I
IH
HIGH Level Input Current
V
CC
=
5.5V, V
IH
=
2.7V
20
µ
A
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IL
=
0.4V
−
0.5
mA
I
O
(Note 3)
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
−
30
−
112
mA
I
OZH
OFF-State Output Current,
V
CC
=
5.5V, V
IH
=
2V,
50
µ
A
HIGH Level Voltage Applied
V
O
=
2.7V,
I
OZL
OFF-State Output Current,
V
CC
=
5.5V, V
IH
=
2V,
−
50
µ
A
LOW Level Voltage Applied
V
O
=
0.4V
I
CC
Supply Current
V
CC
=
5.5V
Outputs HIGH
82
133
Outputs OPEN
Outputs LOW
92
149
mA
Outputs Disabled
100
160
www.fairchildsemi.com
4
DM
74AS874
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
From
To
Min
Max
Units
f
MAX
Maximum Clock Frequency
V
CC
=
4.5V to 5.5V
80
MHz
t
PLH
Propagation Delay Time
R
L
=
500
Ω
Clock
Any Q
3
8.5
ns
LOW-to-HIGH Level Output
C
L
=
50 pF
t
PHL
Propagation Delay Time
Clock
Any Q
4
10.5
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time
Output Control
Any Q
2
7
ns
to HIGH Level Output
t
PZL
Output Enable Time
Output Control
Any Q
3
10.5
ns
to LOW Level Output
t
PHZ
Output Disable Time
Output Control
Any Q
2
6
ns
from HIGH Level Output
t
PLZ
Output Disable Time
Output Control
Any Q
2
7.5
ns
from LOW Level Output
t
PHL
Propagation Delay Time
Clear
Any Q
4
11.5
ns
HIGH-to-LOW Level Output
5
www.fairchildsemi.com
DM74AS874
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
www.fairchildsemi.com
6
DM74AS874
Dual
4-
B
it
D-
T
ype
Edge-
T
ri
ggere
d
Fl
ip-
F
lo
p
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com