July 1997
Revised April 1999
7
4
VH
CT3
73A
Oct
a
l D-T
ype Latch
wit
h
3-ST
A
T
E
Outp
uts
© 1999 Fairchild Semiconductor Corporation
DS500027.prf
www.fairchildsemi.com
74VHCT373A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT373A is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is latched. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
s
High speed: t
PD
=
7.7 ns (typ) at T
A
=
25
°
C
s
High Noise Immunity: V
IH
=
2.0V, V
IL
=
0.8V
s
Power Down Protection is provided on all inputs and
outputs
s
Low Power Dissipation:
I
CC
=
4
µ
A (max) @ T
A
=
25
°
C
s
Pin and Function Compatible with 74HCT373
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74VHCT373AM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHCT373ASJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT373AMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT373AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
D
0
–D
7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O
0
–O
7
3-STATE Outputs
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2
7
4
VH
CT37
3A
Functional Description
The VHCT373A contains eight D-type latches with 3-
STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH-
to-LOW transition of LE. The 3-STATE standard outputs
are controlled by the Output Enable (OE) input. When OE
is LOW, the standard outputs are in the 2-state mode.
When OE is HIGH, the standard outputs are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
LE
OE
D
n
O
n
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
3
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VH
CT3
73A
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 6)
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3: HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4: When outputs are in OFF-State or when V
CC
=
OV.
Note 5: V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active).
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 7: Parameter guaranteed by design.
Supply Voltage (V
CC
)
−
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
−
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
(Note 3)
−
0.5V to V
CC
+
0.5V
(Note 4)
−
0.5V to
+
7.0V
Input Diode Current (I
IK
)
−
20 mA
Output Diode Current (I
OK
)
(Note 5)
±
20 mA
DC Output Current (I
OUT
)
±
25 mA
DC V
CC
/GND Current (I
CC
)
±
75 mA
Storage Temperature (T
STG
)
−
65
°
C to
+
150
°
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
Supply Voltage (V
CC
)
4.5V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
(Note 3)
0V to V
CC
(Note 4)
0V to 5.5V
Operating Temperature (T
OPR
)
−
40
°
C to
+
85
°
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
5.0
±
0.5V
0 ns/V
∼
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
T
A
=
−
40
°
C to
+
85
°
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
4.5
2.0
2.0
V
Input Voltage
5.5
2.0
2.0
V
IL
LOW Level
4.5
0.8
0.8
V
Input Voltage
5.5
0.8
0.8
V
OH
HIGH Level
4.5
4.40
4.50
4.40
V
V
IN
=
V
IH
I
OH
=
−
50
µ
A
Output Voltage
4.5
3.94
3.80
V
or V
IL
I
OH
=
−
8 mA
V
OL
LOW Level
4.5
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
50
µ
A
Output Voltage
4.5
0.36
0.44
V
or V
IL
I
OL
=
8 mA
I
OZ
3-STATE Output
5.5
±
0.25
±
2.5
µ
A
V
IN
=
V
IH
or V
IL
OFF-State Current
V
OUT
=
V
CC
or GND
I
IN
Input Leakage Current
0
−
5.5
±
0.1
±
1.0
µ
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
µ
A
V
IN
=
V
CC
or GND
I
CCT
Maximum I
CC
/Input
5.5
1.35
1.50
mA
V
IN
=
3.4V
Other Inputs
=
V
CC
or GND
I
OFF
Output Leakage Current
0.0
+
0.5
+
0.5
µ
A
V
OUT
=
5.5V
(Power Down State)
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
Units
Conditions
Typ
Limits
V
OLP
Quiet Output Maximum Dynamic V
OL
5.0
1.2
1.6
V
C
L
=
50 pF
(Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0
−
1.2
−
1.6
V
C
L
=
50 pF
(Note 7)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
5.0
2.0
V
C
L
=
50 pF
(Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage
5.0
0.8
V
C
L
=
50 pF
(Note 7)
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4
7
4
VH
CT37
3A
AC Electrical Characteristics
Note 8: Parameter guaranteed by design. t
OSLH
=
|t
PLH
max
−
t
PLH min
|; t
OSHL
=
|t
PHL max
−
t
PHL min
|
Note 9: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
=
C
PD
• V
CC
• f
IN
+
I
CC
/8 (per F/F).
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
T
A
=
−
40
°
C to
+
85
°
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay Time
5.0
±
0.5
7.7
12.3
1.0
13.5
ns
C
L
=
15 pF
t
PHL
(LE to O
n
)
8.5
13.3
1.0
14.5
C
L
=
50 pF
t
PLH
Propagation Delay Time
5.0
±
0.5
5.1
8.5
1.0
9.5
ns
C
L
=
15 pF
t
PHL
(D to O
n
)
5.9
9.5
1.0
10.5
C
L
=
50 pF
t
PZL
3-STATE Output Enable Time
5.0
±
0.5
6.3
10.9
1.0
12.5
ns
R
L
=
1 k
Ω
C
L
=
15 pF
t
PZH
7.1
11.9
1.0
13.5
C
L
=
50 pF
t
PLZ
3-STATE Output Disable Time
5.0
±
0.5
8.8
11.2
1.0
12.0
ns
R
L
=
1 k
Ω
C
L
=
50 pF
t
PHZ
t
OSLH
Output to Output Skew
5.0
±
0.5
1.0
1.0
(Note 8)
t
OSHL
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
OUT
Output Capacitance
6
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
25
pF
(Note 9)
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
T
A
=
−
40
°
C to
+
85
°
C
Units
Min
Typ
Max
Min
Max
t
W
(H)
Minimum Pulse Width (LE)
5.0
±
0.5
6.5
8.5
ns
t
S
Minimum Set-Up Time
5.0
±
0.5
1.5
1.5
ns
t
H
Minimum Hold Time
5.0
±
0.5
3.5
3.5
ns
5
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7
4
VH
CT3
73A
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
7
4
VH
CT37
3A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7
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VH
CT3
73A
Oct
a
l D-T
ype Latch
wit
h
3-ST
A
T
E
Outp
uts
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A