© 1999 Fairchild Semiconductor Corporation
DS010991
www.fairchildsemi.com
May 1992
Revised November 1999
7
4
AB
T2
244 Oct
a
l
Buff
er/
L
in
e Dr
iver
wi
th
25
Ω
Seri
es
Resis
tors
i
n
t
h
e Out
puts
74ABT2244
Octal Buffer/Line Driver with
25
Ω
Series Resistors in the Outputs
General Description
The ABT2244 is an octal buffer and line driver designed to
drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented transmit-
ters/receivers.
The 25
Ω
series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Features
s
Guaranteed latchup protection
s
High impedance glitch-free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Schematic of Each Output
Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Order Number
Package Number
Package Description
74ABT2244CSC M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT2244CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT2244CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT2244CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT2244CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names
Description
OE
1
, OE
2
Output Enable Input
(Active LOW)
I
0
–I
7
Inputs
O
0
–O
7
Outputs
OE
1
I
0–3
O
0–3
OE
2
I
4–7
O
4–7
H
X
Z
H
X
Z
L
H
H
L
H
H
L
L
L
L
L
L
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2
74ABT2244
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
DC Electrical Characteristics
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: For 8 bits toggling, I
CCD
<
0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
Storage Temperature
−
65
°
C to
+
150
°
C
Ambient Temperature under Bias
−
55
°
C to
+
125
°
C
Junction Temperature under Bias
−
55
°
C to
+
150
°
C
V
CC
Pin Potential to Ground Pin
−
0.5V to
+
7.0V
Input Voltage (Note 2)
−
0.5V to
+
7.0V
Input Current (Note 2)
−
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off State
−
0.5V to 5.5V
in the HIGH State
−
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
(Across Comm Operating Range)
−
300 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
−
40
°
C to
+
85
°
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
∆
V/
∆
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
−
1.2
V
Min
I
IN
=
−
18 mA
V
OH
Output HIGH
2.5
V
Min
I
OH
=
−
3 mA
2.0
V
Min
I
OH
=
−
32 mA
V
OL
Output LOW Voltage
0.8
V
Min
I
OL
=
15 mA
I
IH
Input HIGH Current
1
µ
A
Max
V
IN
=
2.7V (Note 4)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
µ
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
−
1
µ
A
Max
V
IN
=
0.5V (Note 4)
−
1
V
IN
=
0.0V
V
ID
Input Leakage Test
475
V
0.0
I
ID
=
1.9
µ
A
All Other Pins Grounded
I
OZH
Output Leakage Current
10
µ
A
0
−
5.5V
V
OUT
=
2.7V; OEn
=
2.0V
I
OZL
Output Leakage Current
−
10
µ
A
0
−
5.5V
V
OUT
=
0.5V; OEn
=
2.0V
I
OS
Output Short-Circuit Current
−
100
−
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output HIGH Leakage Current
50
µ
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
100
µ
A
0.0
V
OUT
=
5.5V; All Others GND
I
CCH
Power Supply Current
50
µ
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
µ
A
Max
OEn
=
V
CC
All Others at V
CC
or GND
I
CCT
Additional
Outputs Enabled
2.5
mA
V
I
=
V
CC
−
2.1V
I
CC
/Input
Outputs 3-STATE
2.5
mA
Max
Enable Input V
I
=
V
CC
−
2.1V
Outputs 3-STATE
50
µ
A
Data Input V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs OPEN
(Note 4)
0.1
MHz
OEn
=
GND (Note 3)
One Bit Toggling, 50% Duty Cycle
3
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7
4
AB
T2
244
AC Electrical Characteristics
(SOIC and SSOP Package)
Capacitance
Note 5: C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
+
25
°
C
T
A
=
−
40
°
C to
+
85
°
C
Units
V
CC
=
+
5V
V
CC
=
4.5V–5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation
1.0
2.2
3.9
1.0
3.9
ns
t
PHL
Delay Data to Outputs
1.0
2.9
4.4
1.0
4.4
t
PZH
Output Enable
1.5
3.7
6.0
1.5
6.0
ns
t
PZL
Time
2.1
4.3
7.0
2.1
7.0
t
PHZ
Output Disable
1.7
3.5
5.8
1.7
5.8
ns
t
PLZ
Time
1.7
3.7
5.8
1.7
5.8
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
°
C
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V
C
OUT
(Note 5)
Output Capacitance
9.0
pF
V
CC
=
5.0V
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4
74ABT2244
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 6. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
5
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7
4
AB
T2
244
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
74ABT2244
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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7
4
AB
T2
244
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
www.fairchildsemi.com
8
74ABT2244
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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7
4
AB
T2
244 Oct
a
l
Buff
er/
L
in
e Dr
iver
wi
th
25
Ω
Seri
es
Resis
tors
i
n
t
h
e Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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