Semiconductor Group
89
•
16 777 216 words by 4-bit organization
•
0 to 70 ˚C operating temperature
•
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
•
Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
•
Single + 3.3 V (
±
0.3V) power supply
•
Low power dissipation
max. 396 active mW ( HYB 3164405J/T(L)-50)
max. 360 active mW ( HYB 3164405J/T(L)-60)
max. 504 active mW ( HYB 3165405J/T(L)-50)
max. 432 active mW ( HYB 3165405J/T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
•
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
•
Hyper page mode (EDO) capability
•
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405J/T(L))
•
4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405J/T(L))
•
Plastic Package:
P-SOJ-34-1 500 mil HYB 3164(5)400J
P-TSOPII-34-1 500 mil HYB 3164(5)400T
HYB 3164405J/T(L) -50/-60
HYB 3165405J/T(L) -50/-60
16M x 4-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
Preliminary Information
Semiconductor Group
90
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
This HYB3164(5)405 is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)405 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB
3164(5)400J/T to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.The HYB3164(5)405TL parts have a very low power „sleep mode“
supported by Self Refresh.
Ordering Information
Pin Names
Type
Ordering
Code
Package
Descriptions
HYB 3164405J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3164405J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3164405T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3164405T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3164405TL-50 on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3164405TL-60 on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3165405J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3165405J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3165405T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3165405T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3165405TL-50 on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3165405TL-60 on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
A0-A12
Address Inputs for HYB 3164405J/T(L)
A0-A11
Address Inputs for HYB 3165405J/T(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O4
Data Input/Output
CAS
Column Address Strobe
WRITE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
91
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Pin Configuration
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Semiconductor Group
92
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR
COL
ADDR
I/O1-
I/O4
Standby
H
H - X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H - L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H - L
L - H
ROW
COL
Data Out, Data In
Hyper Page Mode Read
1st Cycle
L
H - L
H
L
ROW
COL
Data Out
2nd Cycle
L
H - L
H
L
n/a
COL
Data Out
Hyper Page Mode Write 1st Cycle
L
H - L
L
X
ROW
COL
Data In
2nd Cycle
L
H - L
L
X
n/a
COL
Data In
Hyper Page Mode RMW 1st Cycle
L
H - L
H - L
L - H
ROW
COL
Data Out, Data In
2st Cycle
L
H - L
H - L
L - H
n/a
COL
Data Out, Data In
RAS only refresh
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H - L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L
L
L
X
X
n/a
High Impedance
Hidden Refresh
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Self Refresh
(L-version only)
H - L
L
H
X
X
X
High Impedance
Semiconductor Group
93
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3164405J/T(L)
Semiconductor Group
94
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3165405J/T(L)
Semiconductor Group
95
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
T
A
= 0 to 70 ˚C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Input high voltage
V
IH
2.0
Vcc+0.3
V
1)
Input low voltage
V
IL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
V
OH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
V
OL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
V
OH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
V
OL
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
I
I(L)
– 2
2
µ
A
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
I
O(L)
– 2
2
µ
A
Average Vcc supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
I
CC1
–
–
110 (140)
100 (120)
mA
mA
2) 3) 4)
Standby Vcc supply current
(RAS=CAS= Vih)
I
CC2
–
2
mA
–
Semiconductor Group
96
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Average Vcc supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
I
CC3
–
–
110 (140)
100 (120)
mA
mA
2) 4)
Average Vcc supply current,
during
hyperpage mode (EDO):
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling: tHPC=tHPC min.)
I
CC4
–
–
115 (150)
100 (120)
mA
mA
2) 3) 4)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
I
CC5
–
200
A
–
Average Vcc supply current, during CAS-before-
RAS refresh mode:
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
I
CC6
–
–
110 (140)
100 (120)
mA
mA
2) 4)
Self Refresh Current (L-version only)
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
I
CC7
–
400
A
Capacitance
T
A
= 0 to 70 ˚C,
V
CC
= 3.3 V
±
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
C
I1
–
5
pF
Input capacitance (RAS, CAS, WRITE, OE)
C
I2
–
7
pF
I/O capacitance (I/O1-I/O4)
C
IO
–
7
pF
DC Characteristics
(cont’d)
T
A
= 0 to 70 ˚C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Semiconductor Group
97
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
AC Characteristics
5)6)
T
A
= 0 to 70 ˚C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
84
–
104
–
ns
RAS precharge time
t
RP
30
–
40
–
ns
RAS pulse width
t
RAS
50
100k
60
100k
ns
CAS pulse width
t
CAS
8
10k
10
10k
ns
Row address setup time
t
ASR
0
–
0
–
ns
Row address hold time
t
RAH
8
–
10
–
ns
Column address setup time
t
ASC
0
–
0
–
ns
Column address hold time
t
CAH
8
–
10
–
ns
RAS to CAS delay time
t
RCD
12
37
14
45
ns
RAS to column address delay time
t
RAD
10
25
12
30
ns
RAS hold time
t
RSH
8
10
–
ns
CAS hold time
t
CSH
45
50
–
ns
CAS to RAS precharge time
t
CRP
5
–
5
–
ns
Transition time (rise and fall)
t
T
1
50
1
50
ns
7
Refresh period for HYB3164405
t
REF
–
128
–
128
ms
Refresh period for HYB3165405
t
REF
–
64
–
64
ms
Read Cycle
Access time from RAS
t
RAC
–
50
–
60
ns
8, 9
Access time from CAS
t
CAC
–
13
–
15
ns
8, 9
Access time from column address
t
AA
–
25
–
30
ns
8,10
OE access time
t
OEA
–
13
–
15
ns
Column address to RAS lead time
t
RAL
25
–
30
–
ns
Read command setup time
t
RCS
0
–
0
–
ns
Read command hold time
t
RCH
0
–
0
–
ns
11
Read command hold time referenced to
RAS
t
RRH
0
–
0
–
ns
11
Semiconductor Group
98
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
CAS to output in low-Z
t
CLZ
0
–
0
–
ns
8
Output buffer turn-off delay
t
OFF
0
13
0
15
ns
12
Output buffer turn-off delay from OE
t
OEZ
0
13
0
15
ns
12
Data to CAS low delay
t
DZC
0
–
0
–
ns
13
Data to OE low delay
t
DZO
0
–
0
–
ns
13
CAS high to data delay
t
CDD
13
–
15
–
ns
14
OE high to data delay
t
ODD
13
–
15
–
ns
14
Write Cycle
Write command hold time
t
WCH
8
–
10
–
ns
Write command pulse width
t
WP
7
–
10
–
ns
Write command setup time
t
WCS
0
–
0
–
ns
15
Write command to RAS lead time
t
RWL
8
–
10
–
ns
Write command to CAS lead time
t
CWL
8
–
10
–
ns
Data setup time
t
DS
0
–
0
–
ns
16
Data hold time
t
DH
7
–
10
–
ns
16
Read-modify-Write Cycle
Read-write cycle time
t
RWC
111
–
135
–
ns
RAS to WE delay time
t
RWD
67
–
79
–
ns
15
CAS to WE delay time
t
CWD
30
–
34
–
ns
15
Column address to WE delay time
t
AWD
42
–
49
–
ns
15
OE command hold time
t
OEH
7
–
10
–
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
t
HPC
20
–
25
–
ns
CAS precharge time
t
CP
8
–
10
–
ns
Access time from CAS precharge
t
CPA
–
27
–
35
ns
7
Output data hold time
t
COH
5
–
5
–
ns
RAS pulse width in hyper page mode
t
RAS
50
200k
60
200k
ns
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 ˚C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
99
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
CAS precharge to RAS Delay
t
RHCP
27
–
35
–
ns
OE pulse width
t
OEP
7
–
10
–
ns
OE hold time from CAS high
t
OEHC
7
–
10
–
ns
WE pulse width to output disable at CAS
high
t
WPZ
7
–
10
–
ns
Output buffer turn-off delay from WE
t
WPZ
0
10
0
10
ns
Hyper Page Mode (EDO) Read-
modify-Write Cycle
Hyper page mode (EDO) read-write
cycle time
t
PRWC
51
–
66
–
ns
CAS precharge to WE
t
CPWD
41
–
49
–
ns
CAS before RAS refresh cycle
CAS setup time
t
CSR
5
–
5
–
ns
CAS hold time
t
CHR
8
–
10
–
ns
RAS to CAS precharge time
t
RPC
5
–
5
–
ns
Write to RAS precharge time
t
WRP
8
–
10
–
ns
Write hold time referenced to RAS
t
WRH
8
–
10
–
ns
CAS-before-RAS counter test cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
t
CPT
35
–
40
–
ns
Self Refresh Cycle
RAS pulse width during self refresh
t
RASS
100k
_
100k
_
ns
17
RAS precharge time during self refresh
t
RPS
84
_
104
_
ns
17
CAS hold time during self refresh
t
CHS
-50
_
-50
_
ns
17
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 ˚C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
100
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Test Mode
Write command setup time
t
WTS
10
–
10
–
ns
18)
Write command hold time
t
WTH
10
–
10
–
ns
18)
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 ˚C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
Semiconductor Group
101
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Notes:
1) All voltages are referenced to VSS.