®
1
DAC7800, 01, 02
DAC7800
DAC7801
DAC7802
DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are mem-
bers of a new family of monolithic dual 12-bit CMOS
multiplying digital-to-analog converters. The digital
interface speed and the AC multiplying performance
are achieved by using an advanced CMOS process
optimized for data conversion circuits. High stability
on-chip resistors provide true 12-bit integral and dif-
ferential linearity over the wide industrial temperature
range of –40
o
C to +85
o
C.
DAC7800 features a serial interface capable of clock-
ing-in data at a rate of at least 10MHz. Serial data is
clocked (edge triggered) MSB first into a 24-bit shift
register and then latched into each D/A separately or
simultaneously as required by the application. An
asynchronous CLEAR control is provided for power-
on reset or system calibration functions. It is packaged
in a 16-pin 0.3" wide plastic DIP.
DAC7801 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each D/A. Then
both D/As are updated simultaneously. DAC7801 fea-
tures an asynchronous CLEAR control. DAC7801 is
packaged in a 24-pin 0.3" wide plastic DIP.
DAC7802 has a single-buffered 12-bit data word in-
terface. Parallel data is loaded (edge triggered) into the
single D/A register for each D/A. DAC7802 is pack-
aged in a 24-pin 0.3" wide plastic DIP.
FEATURES
q
TWO D/As IN A 0.3" WIDE PACKAGE
q
SINGLE +5V SUPPLY
q
HIGH SPEED DIGITAL INTERFACE:
Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802
q
MONOTONIC OVER TEMPERATURE
q
LOW CROSSTALK: –94dB min
q
FULLY SPECIFIED OVER –40
O
C TO +85
O
C
APPLICATIONS
q
PROCESS CONTROL OUTPUTS
q
ATE PIN ELECTRONICS LEVEL SETTING
q
PROGRAMMABLE FILTERS
q
PROGRAMMABLE GAIN CIRCUITS
q
AUTO-CALIBRATION CIRCUITS
Dual Monolithic CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTERS
Serial Interface
8-Bit Interface
8 Bits + 4 Bits
Serial
DAC7801
DAC7800
12-Bit MDAC
DAC A
FB B
I
OUT B
CLR
WR
A0
CS
A1
UPD
UPD A
UPD B
CS
CLK
CLR
12-Bit MDAC
DAC B
R
12-Bit Interface
DAC7802
CSA
WR
12
8
CSB
12
12
AGND B
REF B
V
FB A
I
OUT A
R
AGND A
REF A
V
®
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1079G
Printed in U.S.A. January, 1998
2
®
DAC7800, 01, 02
SPECIFICATIONS
ELECTRICAL
At V
DD
= +5VDC, V
REF A
= V
REF B
= +10V, T
A
= –40
°
C to +85
°
C, unless otherwise noted.
DAC7800, 7801, 7802K
DAC7800, 7801, 7802L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
12
T
Bits
Relative Accuracy
±
1
±
1/2
LSB
Differential Nonlinearity
±
1
T
LSB
Gain Error
Measured Using R
FB A
and R
FB B
.
±
3
±
1
LSB
All Registers Loaded with All 1s.
Gain Temperature Coefficient
(1)
2
5
T
T
ppm/
°
C
Output Leakage Current
T
A
= +25
°
C
0.005
10
T
T
nA
T
A
= –40
°
C to +85
°
C
3
150
T
T
nA
REFERENCE INPUT
Input Resistance
6
10
14
T
T
T
k
Ω
Input Resistance Match
0.5
3
T
2
%
DIGITAL INPUTS
V
IH
(Input High Voltage)
2
T
V
V
IL
(Input Low Voltage)
0.8
T
V
I
IN
(Input Current)
T
A
= +25
°
C
±
1
T
µ
A
T
A
= –40
°
C to +85
°
C
±
10
T
µ
A
C
IN
(Input Capacitance)
0.8
10
T
T
pF
POWER SUPPLY
V
DD
4.5
5.5
T
T
V
I
DD
0.2
2
T
T
mA
Power Supply Rejection
V
DD
from 4.5V to 5.5V
0.002
T
%/%
T
Same specification as for DAC7800, 7801, 7802K.
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At V
DD
= +5VDC, V
REF A
= V
REF B
= +10V, T
A
= +25
°
C, unless otherwise noted. These specifications are fully characterized but not subject to test.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
NOTE: (1) Guaranteed but not tested.
DAC7800, 7801, 7802K
DAC7800, 7801, 7802L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
OUTPUT CURRENT SETTLING TIME
To 0.01% of Full Scale
0.4
0.8
T
T
µ
s
R
L
= 100
Ω
, C
L
= 13pF
DIGITAL-TO-ANALOG GLITCH IMPULSE
V
REF A
= V
REF B
= 0V
0.9
T
nV-s
R
L
= 100
Ω
, C
L
= 13pF
AC FEEDTHROUGH
f
VREF
= 10kHz
–75
–72
T
T
dB
OUTPUT CAPACITANCE
DAC Loaded with All 0s
30
50
T
T
pF
DAC Loaded with All 1s
70
100
T
T
pF
CHANNEL-TO-CHANNEL ISOLATION
V
REF A
to I
OUT B
f
VREF A
= 10kHz
–90
–94
T
T
dB
V
REF B
= 0V,
Both DACs Loaded with 1s
V
REF B
to I
OUT A
f
VREF B
= 10kHz
–90
–101
T
T
dB
V
REF A
= 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK
Full Scale Transition
0.9
T
nV-s
R
L
= 100
Ω
, C
L
= 13pF
T
Same specification as for DAC7800, 7801, 7802K.
®
3
DAC7800, 01, 02
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER
(1)
RELATIVE ACCURACY
GAIN ERROR
DAC7800KP
16-Pin PDIP
180
±
1LSB
±
3LSB
DAC7800LP
16-Pin PDIP
180
±
1/2LSB
±
1LSB
DAC7800KU
16-Lead SOIC
211
DAC7800LU
16-Lead SOIC
211
DAC7801KP
24-Pin DIP
243
±
1LSB
±
3LSB
DAC7801LP
24-Pin DIP
243
±
1/2LSB
±
1LSB
DAC7801KU
24-Lead SOIC
239
DAC7801LU
24-Lead SOIC
239
DAC7802KP
24-Pin DIP
243-3
±
1LSB
±
3LSB
DAC7802LP
24-Pin DIP
243-3
±
1/2LSB
±
1LSB
DAC7802KU
24-Lead SOIC
239
DAC7802LU
24- Lead SOIC
239
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
V
DD
to AGND ................................................................................. 0V, +7V
V
DD
to DGND ................................................................................. 0V, +7V
AGND to DGND .......................................................................... –0.3, V
DD
Digital Input to DGND ......................................................... –0.3, V
DD
+ 0.3
V
REF A
, V
REF B
to AGND .....................................................................
±
20V
V
REF A
, V
REF B
to DGND .....................................................................
±
20V
I
OUT A
, I
OUT B
to AGND ................................................................. –0.3, V
DD
Storage Temperature Range ........................................... –55
°
C to +125
°
C
Operating Temperature Range .......................................... –40
°
C to +85
°
C
Lead Temperature (soldering, 10s) ................................................ +300
°
C
Junction Temperature ...................................................................... +175
°
C
ABSOLUTE MAXIMUM RATINGS
At T
A
= +25
°
C, unless otherwise noted.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure.
Burr-Brown Corporation recommends that all integrated cir-
cuits be handled and stored using appropriate ESD protection
methods.
Digital Inputs: All digital inputs of the DAC780X family
incorporate on-chip ESD protection circuitry. This protection
is designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500
Ω
)
applied to each digital input.
Analog Pins: Each analog pin has been tested to Burr-Brown’s
analog ESD test consisting of five 1000V positive and nega-
tive discharges (100pF in series with 1500
Ω
) applied to each
pin. AGND, I
OUT
, and R
FB
show some sensitivity. Failure to
observe ESD handling procedures could result in catastrophic
device failure.
4
®
DAC7800, 01, 02
DAC7800
BLOCK DIAGRAM
DAC A
DAC B
DAC A Register
12
12
12
UPD B
I
AGND B
R
V
V
R
I
AGND A
UPD A
OUT B
FB B
REF B
REF A
FB A
OUT A
12
V
DD
9
DGND
10
15
16
14
13
4
3
2
1
6
DAC B Register
Bit 0
Bit 11
Bit 12
Bit 23
Control Logic and Shift Register
7
11
CLR
12
DAC7800
Data
In
5
CLK
8
CS
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AGND A
CLK
UPD A
Data In
CS
AGND B
I
R
V
V
CLR
UPD B
DGND
OUT A
FB A
REF A
OUT B
DAC7800
Top View
DIP
I
R
V
FB B
REF B
DD
Data In
Bit 0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
DAC A
MSB
DAC A
LSB
DAC B
MSB
DAC B
DAC7800 Data Input Sequence
DAC7800 Digital Interface Block Diagram
24-Bit
Shift Register
DAC A Register
UPD A
Data In
CLK
UPD B
LSB
MSB
DAC B Register
LSB
MSB
Bit
23
Bit
12
Bit
11
Bit
0
CLK
DATA INPUT FORMAT
CLK
UPD A
UPD B
CS
CLR
FUNCTION
X
X
X
X
0
All register contents set to 0’s (asynchronous).
X
X
X
1
X
No data transfer.
X
X
0
1
Input data is clocked into input register (location Bit 23) and previous data shifts.
X
0
1
0
1
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A.
X
1
0
0
1
Input register bits 11 (LSB)—0 (MSB) are loaded into DAC B.
X
0
0
0
1
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A, and input register bits 11 (LSB)—0 (MSB)
are loaded into DAC B.
X = Don’t care.
means falling edge triggered.
LOGIC TRUTH TABLE
®
5
DAC7800, 01, 02
DAC7800
(CONT)
DATA
CS
CLK
t
1
t
5
UPD A
UPD B
t
3
t
7
CLR
t
6
t
8
t
4
0V
5V
5V
5V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns. (2) Tim-
ing measurement reference level is V + V
2
F
R
IH
IL
.
t
2
PARAMETER
MINIMUM
t
1
— Data Setup Time
15ns
t
2
— Data Hold Time
15ns
t
3
— Chip Select to CLK,
15ns
Update, Data Setup Time
t
4
— Chip Select to CLK,
40ns
Update, Data Hold Time
t
5
— CLK Pulse Width
40ns
t
6
— Clear Pulse Width
40ns
t
7
— Update Pulse Width
40ns
t
8
— CLK Edge to UPD A
15ns
or UPD B
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40
°
C to +85
°
C.
LOGIC TRUTH TABLE
DAC A
I
AGND A
R
V
V
R
I
AGND B
OUT A
FB A
REF A
REF B
FB B
OUT B
20
V
DD
2
1
3
4
21
22
23
24
DAC A Register
4
8
DAC A
LS
Input
Reg
DAC A
MS
Input
Reg
Control Logic
DAC B
DAC B Register
4
8
12
DGND
DAC B
LS
Input
Reg
DAC B
MS
Input
Reg
19
16
15
5
18
17
UPD
A1
A0
CS
WR
CLR
DAC7801
14
6
DB7–DB0
12
12
BLOCK DIAGRAM
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND A
CS
DB0
DB1
DB2
DB3
DB4
DB5
DGND
AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7801
Top View
DIP
I
R
V
DAC7801
CLR
UPD
CS
WR
A1
A0
FUNCTION
1
1
1
X
X
X
No Data Transfer
1
1
X
1
X
X
No Data Transfer
0
X
X
X
X
X
All Registers Cleared
1
1
0
0
0
0
DAC A LS Input Register Loaded with DB7–DB0 (LSB)
1
1
0
0
0
1
DAC A MS Input Register Loaded with DB3 (MSB)–DB0
1
1
0
0
1
0
DAC B LS Input Register Loaded with DB7–DB0 (LSB)
1
1
0
0
1
1
DAC B MS Input Register Loaded with DB3 (MSB)–DB0
1
0
1
0
X
X
DAC A, DAC B Registers Updated Simultaneously from Input Registers
1
0
0
0
X
X
DAC A, DAC B Registers are Transparent
X = Don’t care.
6
®
DAC7800, 01, 02
CK
DAC B
DAC A
12
12
12
12
12
DGND
18
CS A
5
CS B
20
WR
19
21
V
DD
DAC7802
6
2 I
3 R
OUT A
FB A
23 R
24 I
1 AGND
FB B
OUT B
DAC A Register
CK
DAC B Register
DB11–DB0
4
22
V
V
REF A
REF B
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
R
V
CS A
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DGND
I
R
V
V
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7802
Top View
DIP
TIMING CHARACTERISTICS
At V
DD
= +5V, and T
A
= –40
o
C to +85
o
C.
DATA
5V
0V
5V
5V
CSA, CSB
WR
t
2
t
1
t
3
t
4
t
5
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t = t = 5ns. (2) Timing measurement reference level
is
V + V
2
F
R
IH
IL
.
PARAMETER
MINIMUM
t
1
- Data Setup Time
20ns
t
2
- Data Hold Time
15ns
t
3
- Chip Select to Write Setup Time
30ns
t
4
- Chip Select to Write Hold Time
0ns
t
5
- Write Pulse Width
30ns
LOGIC TRUTH TABLE
CSA
CSB
WR
FUNCTION
X