DAC813

DAC813

25k

Ω

25k

Ω

24.9k

Ω

BPO

20V Span

OUT

REF IN

REF OUT

10V

Reference

12-Bit D/A

Converter

D/A Latch

Input Latch

Reset

4 MSBs

8 LSBs

49.5k

Ω

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

DAC813

Microprocessor-Compatible

12-BIT DIGITAL-TO-ANALOG CONVERTER

FEATURES

1/2LSB NONLINEARITY OVER

TEMPERATURE

GUARANTEED MONOTONIC OVER

TEMPERATURE

LOW POWER: 270mW typ

DIGITAL INTERFACE DOUBLE

BUFFERED: 12 AND 8 + 4 BITS

SPECIFIED AT

12V AND

15V POWER

SUPPLIES

RESET FUNCTION TO BIPOLAR ZERO

0.3" WIDE DIP AND SO PACKAGES

DESCRIPTION

The DAC813 is a complete monolithic 12-bit digital-

to-analog converter with a flexible digital interface.

It includes a precision +10V reference, interface con-

trol logic, double-buffered latch and a 12-bit D/A

converter with voltage output operational amplifier.

Fast current switches and laser-trimmed thin-film

resistors provide a highly accurate, fast D/A con-

verter.

Digital interfacing is facilitated by a double buffered

latch. The input latch consists of one 8-bit byte and

one 4-bit nibble to allow interfacing to 8-bit (right

justified format) or 16-bit data buses. Input gating

logic is designed so that the last nibble or byte to be

loaded can be loaded simultaneously with the transfer

of data to the D/A latch saving computer instructions.

A reset control allows the DAC813 D/A latch to

asynchronously reset the D/A output to bipolar zero,

a feature useful for power-up reset, recalibration, or

for system re-initialization upon system failure.

The DAC813 is specified to

1/2LSB maximum lin-

earity error (J, A grades) and

1/4LSB (K grade).

It is packaged in 28-pin 0.3" wide plastic DIP and

28-lead plastic SOIC

PDS-1077G

Printed in U.S.A. March, 1998

DAC813

DAC813JP, JU, AU

DAC813KP, KU

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DIGITAL INPUTS

Resolution

Bits

Codes

(1)

USB, BOB

Digital Inputs Over Temperature Range

(2)

(3)

+5.5

VDC

+0.8

VDC

DATA Bits, WR, Reset, LDAC, LMSB, LLSB

= +2.7V

= +0.4V

ACCURACY

Linearity Error

1/4

1/2

1/8

1/4

LSB

Differential Linearity Error

1/2

3/4

1/4

1/2

LSB

Gain Error

(4)

0.05

0.2

Unipolar Offset Error

(5)

0.01

0.02

% of FSR

(7)

Bipolar Zero Error

(6)

0.02

0.2

% of FSR

Monotonicity

Guaranteed

Power Supply Sensitivity: +V

20V Range

ppm of FSR/%

–V

ppm of FSR/%

DRIFT

Over Specification

Gain

Temperature Range

ppm/

Unipolar Offset

ppm of FSR/

Bipolar Zero

ppm of FSR/

Linearity Error Over Temperature Range

1/2

3/4

1/4

1/2

LSB

Monotonicity Over Temperature Range

Guaranteed

SETTLING TIME

(8)

(To Within

0.01% of

FSR of Final Value; 5k

Ω

|| 500pF load)

For Full Scale Range Change

20V Range

4.5

10V Range

3.3

For 1LSB Change at Major Carry

(9)

Slew Rate

ANALOG OUTPUT

Voltage Range: Unipolar

11.4V

0 to +10

Bipolar

11.4V

Output Current

Output Impedance

At DC

0.2

Ω

Short Circuit to Common Duration

Indefinite

REFERENCE VOLTAGE

Voltage

+9.95

+10

+10.05

Source Current Available for External Loads

Impedance

Ω

Temperature Coefficient

ppm/

Short Circuit to Common Duration

Indefinite

POWER SUPPLY REQUIREMENTS

Voltage: +V

+11.4

+15

+16.5

VDC

–V

–11.4

–15

–16.5

VDC

Current: +V

+ V

No Load

–V

No Load

–5

–7

Potential at DCOM with Respect to ACOM

(10)

–3

Power Dissipation

270

330

TEMPERATURE RANGE

Specification: J, K

+70

–40

+85

Operating: J, K

–40

+85

–55

+125

Storage: J, K

–60

+100

–65

+150

Same as specification for DAC813AU, JP, JU.

NOTES: (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. (2) TTL and 5V CMOS compatible. (3) Open DATA input lines will be pulled above +5.5V.

See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) Specified with 500

Ω

Pin 6 to 7. Adjustable to zero with external trim

potentiometer. (5) Error at input code 000

HEX

for unipolar mode, FSR = 10V. (6) Error at input code 800

HEX

for bipolar range. Specified with 100

Ω

Pin 6 to 4 and

with 500

Ω

pin 6 to 7. See page 9 for zero adjustment procedure. (7) FSR means Full Scale Range and is 20V for the

10V range. (8) Maximum represents the

limit. Not 100% tested for this parameter. (9) At the major carry, 7FF

HEX

to 800

HEX

and 800

HEX

to 7FF

HEX

. (10) The maximum voltage at which ACOM and DCOM

may be separated without affecting accuracy specifications.

SPECIFICATIONS

At T

= +25

12V or

15V and load on V

OUT

= 5k

Ω

|| 500pF to common, unless otherwise noted.

DAC813

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

to ACOM .......................................................................... 0 to +18V

–V

to ACOM .......................................................................... 0 to –18V

to –V

............................................................................ 0 to +36V

DCOM with respect to ACOM .............................................................

Digital Inputs (Pins 11–15, 17–28) to DCOM .................... –0.5V to +V

External Voltage Applied to BPO Span Resistor ..............................

REF OUT

........................................................... Indefinite Short to ACOM

OUT

................................................................. Indefinite Short to ACOM

Power Dissipation .......................................................................... 750mW

Lead Temperature (soldering, 10s) ............................................... +300

Max Junction Temperature ............................................................ +165

Thermal Resistance,

J-A

:Plastic DIP and SOIC ........................ 130

C/W

Ceramic DIP ......................................... 85

C/W

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

PIN

NAME

DESCRIPTION

Positive supply pin for logic circuits. Connect to +V

2, 3

20V Range

Connect Pin 2 or Pin 3 to Pin 9 (V

OUT

) for a 20V

FSR. Connect both to Pin 9 for a 10V FSR.

BPO

Bipolar offset. Connect to Pin 6 (V

REF OUT

) through

100

Ω

resistor or 200

Ω

potentiometer for bipolar

operation.

ACOM

Analog common,

supply return.

REF OUT

+10V reference output referred to ACOM.

REF IN

Connected to V

REF OUT

through a 1k

Ω

gain

adjustment potentiometer or a 500

Ω

resistor.

Analog supply input, nominally +12V to +15V

referred to ACOM.

OUT

D/A converter voltage output.

–V

Analog supply input, nominally –12V or –15V

referred to ACOM.

Master enable for LDAC, LLSB, and LMSB. Must

be low for data transfer to any latch.

LDAC

Load DAC. Must be low with WR for data transfer

to the D/A latch and simultaneous update of the

D/A converter.

Reset

When low, resets the D/A latch such that a Bipolar

Zero output is produced. This control overrides all

other data input operations.

LMSB

Enable for 4-bit input latch of D

-D

data inputs.

NOTE: This logic path is slower than the WR path.

LLSB

Enable for 8-bit input latch of D

-D

data inputs.

NOTE: This logic path is slower than the WR path.

DCOM

Digital common.

Data Bit 1, LSB.

Data Bit 2.

Data Bit 3.

Data Bit 4.

Data Bit 5.

Data Bit 6.

Data Bit 7.

Data Bit 8.

Data Bit 9.

Data Bit 10.

D10

Data Bit 11.

D11

Data Bit 12, MSB, positive true.

PIN DESCRIPTIONS

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-

formance degradation to complete device failure. Burr-

Brown Corporation recommends that all integrated circuits

be handled and stored using appropriate ESD protection

methods.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

LINEARITY

GAIN

DRAWING

TEMPERATURE

ERROR, MAX

DRIFT

PRODUCT

PACKAGE

NUMBER

(1)

RANGE

AT +25

C (LSB)

(ppm/

DAC813JP

28-Pin Plastic DIP

246

C to +70

1/2

DAC813JU

28-Lead Plastic SOIC

217

C to +70

1/2

DAC813KP

28-Pin Plastic DIP

246

C to +70

1/4

DAC813KU

28-Lead Plastic SOIC

217

C to +70

1/4

DAC813AU

28-Lead Plastic SOIC

217

–40

C to +85

1/2

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

DAC813

MAJOR CARRY GLITCH

Time (µs)

OUT

(mV)

250

200

150

100

–2

+10

WR (V)

Data =

7FF

Data = 800

Data = 7FF

–5

–10

–15

Time (µs)

± FULL SCALE OUTPUT SWING

V (V)

OUT

WR (V)

0.5

–0.5

000

Input Code (Hexidecimal)

INTEGRAL LINEARITY ERROR

Linearity Error (LSB)

400

800

C00

FFF

0.5

–0.5

–1

–60

–20

100

140

Temperature (°C)

CHANGE OF GAIN AND OFFSET ERROR

vs TEMPERATURE

0.8

0.4

–0.4

–0.8

Gain Error

Bipolar

Offset

Unipolar

Offset

Bipolar/Unipolar Offset (%)

(For 10V FSR; Double for 20V FSR)

∆

Gain Error (%)

∆

–2

–4

Input Current (µA)

–2

Input Voltage (V)

DIGITAL INPUT CURRENT

vs INPUT VOLTAGE

LMSB, LDAC

Reset

LLSB, WR

Data

Frequency (Hz)

[Change in FSR]/[Change in Supply Voltage]

100

10k

100k

POWER SUPPLY REJECTION vs

POWER SUPPLY RIPPLE FREQUENCY

(ppm of FSR/ %)

100

0.1

–V

TYPICAL PERFORMANCE CURVES

At T

= +25

C, V

15V, unless otherwise noted.

DAC813

–10

–20

–40

Around +10V (mV)

–2

Time (µs)

SETTLING TIME, –10V TO +10V

∆

WR (V)

OUT

1LSB = 4.88mV

–10

–20

Around –10V (mV)

–2

Time (µs)

SETTLING TIME, +10V TO –10V

WR (V)

∆

1LSB = 4.88mV

OUT

TYPICAL PERFORMANCE CURVES

(CONT)

At T

= +25

C, V

15V, unless otherwise noted.

DISCUSSION OF

SPECIFICATIONS

INPUT CODES

The DAC813 accepts positive-true binary input codes.

DAC813 may be connected by the user for any one of the

following codes: USB (Unipolar Straight Binary), BOB

(Bipolar Offset Binary) or, using an external inverter on the

MSB line, BTC (Binary Two’s Complement). See Table I.

MONOTONICITY

A D/A converter is monotonic if the output either increases

or remains the same for increasing digital inputs. All grades

of DAC813 are monotonic over their specification tempera-

ture range.

DRIFT

Gain Drift is a measure of the change in the Full Scale Range

(FSR) output over the specification temperature range. Gain

Drift is expressed in parts per million per degree Celsius

(ppm/

C).

Unipolar Offset Drift is measured with a data input of

000

HEX

. The D/A is configured for unipolar output. Unipolar

Offset Drift is expressed in parts per million of Full Scale

Range per degree Celsius (ppm of FSR/

C).

Bipolar Zero Drift is measured with a data input of 800

HEX

The D/A is configured for bipolar output. Bipolar Zero Drift

is expressed in parts per million of Full Scale Range per

degree Celsius (ppm of FSR/

C).

SETTLING TIME

Settling Time is the total time (including slew time) for the

output to settle within an error band around its final value

after a change in input. Three settling times are specified to

0.012% of Full Scale Range (FSR): two for maximum full

scale range changes of 20V and 10V, and one for a 1LSB

change. The 1LSB change is measured at the major carry

(7FF

HEX

to 800

HEX

and 800

HEX

to 7FF

HEX

), the input tran-

sition at which worst-case settling time occurs.

REFERENCE SUPPLY

DAC813 contains an on-chip +10V reference. This voltage

(pin 6) has a tolerance of

50mV. V

REF OUT

must be con-

nected to V

REF IN

through a gain adjust resistor with a

nominal value of 500

Ω

. The connection can be made through

an optional 1k

Ω

trim resistor to provide adjustment to zero

DIGITAL

ANALOG OUTPUT

INPUT

USB

BOB

BTC*

Unipolar

Bipolar

Binary

Straight

Offset

Two’s

MSB to LSB

Binary

Complement

FFF

HEX

+ Full Scale

Zero – 1LSB

800

HEX

+ 1/2 Full Scale

Zero

– Full Scale

7FF

HEX

+ 1/2 Full Scale – 1LSB

Zero – 1LSB

+ Full Scale

000

HEX

Zero

– Full Scale

Zero

* Invert MSB of BOB code with external inverter to obtain BTC code.

TABLE I. Digital Input Codes.

LINEARITY ERROR

Linearity error as used in D/A converter specifications by

Burr-Brown is the deviation of the analog output from a

straight line drawn between the end points (inputs all “1s”

and all “0s”). The DAC813 linearity error is specified at

1/4LSB (max) at +25

C K grades, and

1/2LSB (max) for

J grades.

DIFFERENTIAL LINEARITY ERROR

Differential linearity error (DLE) is the deviation from a

1LSB output change from one adjacent state to the next. A

DLE specification of 1/2LSB means that the output step size

can range from 1/2LSB to 3/2LSB when the input changes

from one state to the next. Monotonicity requires that DLE

be less than 1LSB over the temperature range of interest.

DAC813

gain error. The reference output may be used to drive

external loads, sourcing at least 5mA. This current should be

constant, otherwise the gain of the converter will vary.

POWER SUPPLY SENSITIVITY

Power supply sensitivity is a measure of the effect of a

power supply change on the D/A converter output. It is

defined as a ppm of FSR output change per percent of

change in either +V

or –V

about the nominal voltages

expressed in ppm of FSR/%. The first performance curve on

page 5 shows typical power supply rejection versus power

supply ripple frequency.

OPERATION

DAC813 is a complete single IC chip 12-bit D/A converter.

The chip contains a 12-bit D/A converter, voltage reference,

output amplifier, and microcomputer-compatible input logic

as shown in Figure 1.

INTERFACE LOGIC

Input latches hold data temporarily while a complete 12-bit

word is assembled before loading into the D/A latch. This

double-buffered organization prevents the generation of spu-

rious analog output values. Each latch is independently

addressable.

All latches are level-triggered. Data present when the con-

trol signals are logic “0” will enter the latch. When any one

of the control signals returns to logic “1”, the data is latched.

A tr