1
®
ADS7831
ADS7831
DESCRIPTION
The ADS7831 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit capacitor-based SAR A/D with inher-
ent S/H, reference, clock, interface for microprocessor
use, and three-state output drivers.
The ADS7831 is specified at a 600kHz sampling rate,
and guaranteed over the full temperature range. A
±
2.5V input range and excellent Nyquist performance
provide an optimum solution in
±
5V supply systems.
The 28-pin ADS7831 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40
°
C to +85
°
C range.
FPO
ADS7831
ADS7831
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation
PDS-1275
Printed in U.S.A. March, 1995
FEATURES
q
600kHz THROUGHPUT RATE
q
STANDARD
±
2.5V INPUT RANGE
q
69dB min SINAD WITH 250kHz INPUT
q
COMPLETE WITH S/H, REF, CLOCK, ETC.
q
PARALLEL DATA w/LATCHES
q
FULLY SPECIFIED –40
°
C TO +85
°
C
q
15MHz –3dB BANDWIDTH
q
28-PIN 0.3" PDIP AND SOIC
12-Bit 600kHz Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
THD : –91dB
SNR :
72dB
SFDR :
94dB
2nd Harmonic : –98dB
3rd Harmonic : –94dB
SFDR: 94dBc
3
Frequency (kHz)
Amplitude (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
300
FREQUENCY SPECTRUM
(16384 Point FFT; f
IN
= 250kHz, –0.5dB)
75
150
225
2
®
2
®
ADS7831
ADS7831P, U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
ANALOG INPUT
Voltage Range
±
2.5
V
Impedance
3.1
k
Ω
Capacitance
5
pF
THROUGHPUT SPEED
Conversion Time
1.3
µ
s
Complete Cycle
Acquire & Convert
1.66
µ
s
Throughput Rate
600
kHz
DC ACCURACY
Integral Linearity Error
±
1
LSB
(1)
Differential Linearity Error
±
1
LSB
No Missing Codes
Guaranteed
Total Unadjusted Error
(2, 3)
±
10
LSB
(Includes Bipolar Zero Error and Full Scale Error)
Power Supply Sensitivity
(+V
DIG
= +V
ANA
= V
D
)
+4.75V < V
D
< +5.25V
±
5
LSB
–5.25V < –V
ANA
< –4.75V
AC ACCURACY
Spurious-Free Dynamic Range
f
IN
= 250kHz
77
87
dB
(4)
Total Harmonic Distortion
f
IN
= 250kHz
–85
–77
dB
Signal-to-(Noise+Distortion)
f
IN
= 250kHz
69
71
dB
Signal-to-Noise
f
IN
= 250kHz
69
72
dB
Usable Bandwidth
(5)
1.6
MHz
Full-Power Bandwidth
15
MHz
SAMPLING DYNAMICS
Aperture Delay
20
ns
Aperture Jitter
10
ps
Transient Response
FS Step
200
ns
Overvoltage Recovery
(6)
250
ns
REFERENCE
Reference Voltage
2.45
2.5
2.55
V
Reference DC Source Current
100
µ
A
(External load should be static)
DIGITAL INPUTS
Logic Levels
V
IL
–0.3
+0.8
V
V
IH
+2.4
V
D
+ 0.3
V
I
IL
V
IL
= 0V
±
10
µ
A
I
IH
V
IH
= 5V
±
10
µ
A
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
I
SINK
= 1.6mA
+0.4
V
V
OH
I
SOURCE
= 500
µ
A
+2.8
V
Leakage Current
High-Z State,
±
5
µ
A
V
OUT
= 0V to V
DIG
Output Capacitance
High-Z State
15
pF
DIGITAL TIMING
Bus Access Time
62
ns
Bus Relinquish Time
83
ns
POWER SUPPLIES
Specified Performance
+V
DIG
= +V
ANA
+4.75
+5
+5.25
V
–V
ANA
–5.25
–5
–4.75
V
+I
DIG
+16
mA
+I
ANA
+16
mA
–I
ANA
–12
mA
Power Dissipation
f
S
= 600kHz
220
275
mW
TEMPERATURE RANGE
Specified Performance
–40
+85
°
C
Storage
–65
+150
°
C
Thermal Resistance (
θ
JA
)
Plastic DIP
75
°
C/W
SOIC
75
°
C/W
NOTES: (1) LSB means Least Significant Bit. For the 12-bit,
±
2.5V input ADS7831, one LSB is 1.22mV. (2) Measured with 50
Ω
in series with analog input. Adjustable
to zero with external potentiometers. (3) Total unadjusted error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code
transitions and includes the effect of offset error. (4) All specifications in dB are referred to a full-scale
±
2.5V input. (5) Usable Bandwidth defined as Full-Scale input
frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. 6) Recovers to specified performance after 2 x FS input over voltage.
SPECIFICATIONS
At T
A
= –40
°
C to +85
°
C, f
S
= 600kHz, +V
DIG
= +V
ANA
= +5V, –V
ANA
= –5V, using internal reference and the 50
Ω
input resistor shown in Figure 4b, unless otherwise specified.
Parallel 12-bits
Binary Two's Complement
3
®
ADS7831
BLOCK DIAGRAM
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: V
IN
..............................................................................
±
25V
REF ..................................... +V
ANA
+0.3V to AGND2 –0.3V
CAP ........................................... Indefinite Short to AGND2
Momentary Short to +V
ANA
Ground Voltage Differences: DGND, AGND1, AGND2 ...................
±
0.3V
+V
ANA
.................................................................................................... +7V
+V
DIG
to +V
ANA
................................................................................... +0.3V
+V
DIG
...................................................................................................... 7V
–V
ANA
.................................................................................................... –7V
Digital Inputs ............................................................. –0.3V to +V
DIG
+0.3V
Maximum Junction Temperature ................................................... +165
°
C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300
°
C
PACKAGE AND ORDERING INFORMATION
(1)
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
ADS7831P
28-Pin Plastic DIP
246
ADS7831U
28-Pin SOIC
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
CDAC
Internal
Ref
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
BUSY
±2.5V Input
2.5V Ref Out
Comparator
Buffer
2.5k
Ω
575
Ω
Successive Approximation Register and Control Logic
Clock
Cap
8.6k
Ω
4.8k
Ω
18k
Ω
4
®
ADS7831
PIN ASSIGNMENTS
DIGITAL
PIN #
NAME
I/O
DESCRIPTION
1
V
IN
Analog Input. Connect via 50
Ω
to analog input. Full-scale input range is
±
2.5V.
2
AGND1
Analog Ground. Used internally as ground reference point. Minimal current flow.
3
REF
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1
µ
F ceramic capacitor.
4
CAP
Reference Buffer Output. 10
µ
F tantalum capacitor to ground. Nominally +2V.
5
AGND2
Analog Ground.
6
D11 (MSB)
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
7
D10
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
8
D9
O
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
9
D8
O
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
10
D7
O
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
11
D6
O
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
12
D5
O
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
13
D4
O
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
14
DGND
Digital Ground.
15
D3
O
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
16
D2
O
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
17
D1
O
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
18
D0 (LSB)
O
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
19
Not internally connected.
20
+V
ANA
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
21
+V
DIG
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
22
DGND
Digital ground.
23
R/C
I
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
24
CS
I
Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH and no conversion
in progress, a falling edge on CS will enable the output data bits.
25
BUSY
O
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
26
–V
ANA
Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1
µ
F ceramic and 10
µ
F tantalum
capacitors.
27
+V
DIG
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
28
+V
ANA
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1
µ
F ceramic and 10
µ
F tantalum capacitors.
PIN CONFIGURATION
Top View
DIP/SOIC
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
+V
ANA
+V
DIG
–V
ANA
BUSY
CS
R/C
DGND
+V
DIG
+V
ANA
NC
(1)
D0 (LSB)
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7831
NOTE: (1) Not Internally Connected.
5
®
ADS7831
TYPICAL PERFORMANCE CURVES
T = +25
°
C, f
S
=600kHz, +V
DIG
= +V
ANA
= +5V, –V
ANA
= –5V, using internal reference and the 50
Ω
input resistor shown in Figure 4b, unless otherwise specified.
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.002MHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
0
75
150
225
300
FREQUENCY SPECTRUM
(4096 Point FFT; f1
IN
= 232kHz, –6.5dB;
f2
IN
= 272kHz, –6.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
0
75
150
225
300
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 252kHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
0
75
150
225
300
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 502kHz, –0.5dB)
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
0
75
150
225
300
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (f
IN
= –0.5dB)
90
80
70
60
50
40
30
20
10
SINAD (dB)
1k
10k
100k
1M
10M
Input Signal Frequency (Hz)
A.C. PARAMETERS vs TEMPERATURE
(f
IN
= 250kHz, –0.5dB)
100
95
90
85
80
75
70
65
60
SFDR, SNR, and SINAD (dB)
THD (dB)
–75
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
SINAD
THD
SNR
SFDR
6
®
ADS7831
TYPICAL PERFORMANCE CURVES
(CONT)
T = +25
°
C, f
S
=600kHz, +V
DIG
= +V
ANA
= +5V, –V
ANA
= –5V, using internal reference and the 50
Ω
input resistor shown in Figure 4b, unless otherwise specified.
0
4095
3584
3072
2560
2048
1536
1024
512
Decimal Code
0
4095
3584
3072
2560
2048
1536
1024
512
Decimal Code
All Codes INL
All Codes DNL
1
0.5
0
–0.5
–1
12 Bit LSBs
12 Bit LSBs
1
0.5
0
–0.5
–1
D.C. PARAMETERS vs. TEMPERATURE
Percent
From Ideal
Percent
From Ideal
–F
S
Error
+F
S
Error
Temperature (
°
C)
–75
Offset Error
0.2
0.1
0
–0.1
–0.2
0.2
0.1
0
–0.1
–0.2
2
1
0
–1
–2
LSBs
From Ideal
50
25
–50
–25
0
75
100
125
150
CODE TRANSITION NOISE
Analog Input Voltage – Expected Code Center (LSBs)
0
100
75
50
25
Conversions Yielding Expected Code (%)
0
1
0.25
0.5
0.75
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
–75
–50
–25
0
25
50
75
100
125
150
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
Internal Reference (V)
Temperature (°C)
CONVERSION TIME (t
7
) vs TEMPERATURE
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
–75
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
Conversion Time (ns)
7
®
ADS7831
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
FIGURE 1. Basic Operation
CS
R/C
BUSY
OPERATION
1
X
X
None. Databus in Hi-Z state.
↓
0
1
Initiates conversion. Databus remains in
Hi-Z state.
0
↓
1
Initiates conversion. Databus enters Hi-Z
state.
0
1
↑
Conversion completed. Valid data from the
most recent conversion on the databus.
↓
1
1
Enables databus with valid data from the
most recent conversion.
↓
1
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
0
↑
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
0
0
↑
Conversion completed. Valid data from the
most recent conversion in the output register,
but the output pins D11-D0 remain tri-stated.
X
X
0
New convert commands ignored. Conversion
in progress.
Table I. Control Line Functions for ‘read’ and ‘convert’.
DESCRIPTION
ANALOG INPUT
DIGITAL INPUT
BINARY TWO'S COMPLEMENT
Full Scale Range
±
2.5V
Least Significant
1.22mV
Bit (LSB)
BINARY CODE
HEX CODE
+Full Scale
2.499V
0111 1111 1111
7FF
(2.5V – 1LSB)
Midscale
0V
0000 0000 0000
000
One LSB below
–1.22mV
1111 1111 1111
FFF
Midscale
–Full Scale
–2.5V
1000 0000 0000
800
TABLE II. Ideal Input Voltages and Output Codes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7831
50
Ω
±2.5V
–5V
+5V
0.1µF
NC
10µF
+
0.1µF
+
10µF
Convert Pulse
40ns min
D0 (LSB)
D1
D2
D3
D6
D5
D4
D7
D8
D9
D10
D11 (MSB)
0.1µF 10µF
+
BUSY
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7831.
Taking R/C (pin 23) LOW for 40ns will initiate a conver-
sion. BUSY (pin 25) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Binary Two’s Complement
with the MSB on D11 (pin 6). BUSY going HIGH can be
used to latch the data. All convert commands will be ignored
while BUSY is LOW.
The ADS7831 will begin tracking the input signal at the end
of the conversion. Allowing 1.66
µ
s between convert com-
mands assures accurate acquisition of a new signal.
STARTING A
CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for a
minimum of 40ns immediately puts the sample/hold of the
ADS7831 in the hold state and starts a conversion. BUSY (pin
25) will go LOW and stay LOW until the conversion is
completed and the internal output register has been updated. All
new convert commands during BUSY LOW will be ignored.
The ADS7831 will begin tracking the input signal at the end
of the conversion. Allowing 1.66
µ
s between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
8
®
ADS7831
t
9
Hi-Z State
t
8