ADS7821

ADS7821

FEATURES

100kHz min SAMPLING RATE

0 to +5V INPUT RANGE

86dB min SINAD WITH 20kHz INPUT

DNL: 16-bits “No Missing Codes”

SINGLE +5V SUPPLY OPERATION

PIN-COMPATIBLE WITH 12-BIT ADS7820

USES INTERNAL OR EXTERNAL

REFERENCE

FULL PARALLEL DATA OUTPUT

100mW max POWER DISSIPATION

28-PIN 0.3" PLASTIC DIP AND SOIC

ADS7821

DESCRIPTION

The ADS7821 is a complete 16-bit sampling A/D

using state-of-the-art CMOS structures. It contains a

complete 16-bit, capacitor-based, SAR A/D with S/H,

reference, clock, interface for microprocessor use, and

three-state output drivers.

The ADS7821 is specified at a 100kHz sampling rate,

and guaranteed over the full temperature range. Laser-

trimmed scaling resistors provide a 0 to +5V input

range, with power dissipation under 100mW.

The 28-pin ADS7821 is available in a plastic 0.3" DIP

and in an SOIC, both fully specified for operation over

the –25

C to +85

C range.

16-Bit 10

s Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

Successive Approximation Register and Control Logic

Clock

Output

Latches

and

Three

State

Drivers

Three

State

Parallel

Data

Bus

BUSY

Comparator

BYTE

R/C

CDAC

Internal

+2.5V Ref

Buffer

Ω

0 to +5V Input

REF

CAP

Ω

20k

Ω

6.66k

Ω

1996 Burr-Brown Corporation

PDS-1323A

Printed in U.S.A. June, 1996

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

ADS7821

SPECIFICATIONS

ELECTRICAL

= –25

C to +85

C, f

= 100kHz, V

DIG

= V

ANA

= V

= +5V, using external reference, unless otherwise specified.

ADS7821P, U

ADS7821PB, UB

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

Parallel 16 bits

Straight Binary

RESOLUTION

Bits

ANALOG INPUT

Voltage Range

0 to +5

Impedance

Ω

Capacitance

THROUGHPUT SPEED

Conversion Cycle

Acquire and Convert

Throughput Rate

100

kHz

DC ACCURACY

Integral Linearity Error

LSB

(1)

No Missing Codes

Bits

Transition Noise

(2)

0.9

LSB

Full Scale Error

(3,4)

0.5

0.25

Full Scale Error Drift

ppm/

Full Scale Error

(3,4)

Internal Reference

0.5

0.25

Full Scale Error Drift

Internal Reference

ppm/

Offset Error

Offset Error Drift

ppm/

Power Supply Sensitivity

+4.75V < V

< +5.25V

LSB

DIG

= V

ANA

= V

)

AC ACCURACY

Spurious-Free Dynamic Range

= 20kHz

(5)

Total Harmonic Distortion

= 20kHz

–90

–94

Signal-to-(Noise+Distortion)

= 20kHz

= –60dB Input

Signal-to-Noise

= 20kHz

Full-Power Bandwidth

(6)

250

kHz

SAMPLING DYNAMICS

Aperture Delay

Transient Response

FS Step

Overvoltage Recovery

(7)

150

REFERENCE

Internal Reference Voltage

2.48

2.5

2.52

Internal Reference Source Current

(Must use external buffer)

Internal Reference Drift

ppm/

External Reference Voltage Range

2.3

2.5

2.7

for Specified Linearity

External Reference Current Drain

Ext. 2.5000V Ref

100

DIGITAL INPUTS

Logic Levels

–0.3

+0.8

+2.0

+0.3V

DIGITAL OUTPUTS

Data Format

Data Coding

SINK

= 1.6mA

+0.4

SOURCE

= 500

Leakage Current

High-Z State,

OUT

= 0V to V

DIG

Output Capacitance

High-Z State

DIGITAL TIMING

Bus Access Time

Bus Relinquish Time

ADS7821

POWER SUPPLIES

Specified Performance

DIG

Must be

≤

ANA

+4.75

+5.25

ANA

+4.75

+5.25

DIG

0.3

ANA

Power Dissipation

= 100kHz

100

TEMPERATURE RANGE

Specified Performance

–25

+85

Derated Performance

–55

+125

Storage

–65

+150

Thermal Resistance (

)

Plastic DIP

C/W

SOIC

C/W

NOTES: (1) LSB means Least Significant Bit. For the 16-bit, 0 to +5V input ADS721, one LSB is 76

V. (2) Typical rms noise at worst case transitions and

temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 6a. (4) Full scale error is the worst case of Full Scale untrimmed deviation from

ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Full-

Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified

performance after 2 x FS input overvoltage.

SPECIFICATIONS

(CONT)

ELECTRICAL

= –25

C to +85

C, f

= 100kHz, V

DIG

= V

ANA

= V

= +5V, using external reference, unless otherwise specified.

ADS7821P, U

ADS7821PB, UB

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ABSOLUTE MAXIMUM RATINGS

Analog Inputs: V

...................................................... –0.7V to V

ANA

+0.3V

REF ................................... AGND2 –0.3V to +V

ANA

+0.3V

CAP .......................................... Indefinite Short to AGND2,

Momentary Short to V

ANA

Ground Voltage Differences: DGND, AGND1, AGND2 ...................

0.3V

ANA

....................................................................................................... 7V

DIG

to V

ANA

..................................................................................... +0.3V

DIG

....................................................................................................... 7V

Digital Inputs ............................................................ –0.3V to +V

DIG

+0.3V

Maximum Junction Temperature ................................................... +165

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s) ................................................ +300

PACKAGE INFORMATION

PACKAGE DRAWING

PRODUCT

PACKAGE

NUMBER

(1)

ADS7821P

Plastic DIP

246

ADS7821PB

Plastic DIP

246

ADS7821U

SOIC

217

ADS7821UB

SOIC

217

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

MINIMUM

SIGNAL-TO-

MAXIMUM

(NOISE +

SPECIFICATION

LINEARITY

DISTORTION)

TEMPERATURE

PRODUCT

ERROR (LSB)

RATIO (dB)

RANGE

PACKAGE

ADS7821P

–25

C to +85

Plastic DIP

ADS7821PB

–25

C to +85

Plastic DIP

ADS7821U

–25

C to +85

SOIC

ADS7821UB

–25

C to +85

SOIC

ORDERING INFORMATION

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-

formance degradation to complete device failure. Burr-

Brown Corporation recommends that all integrated circuits

be handled and stored using appropriate ESD protection

methods.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

ADS7821

Analog Input.

AGND1

Analog Ground. Used internally as ground reference point.

REF

Reference Input/Output. 2.2

F tantalum capacitor to ground.

CAP

Reference Buffer Capacitor. 2.2

F tantalum capacitor to ground.

AGND2

Analog Ground.

D15 (MSB)

Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

D14

Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW.

D13

Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW.

D12

Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW.

D11

Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW.

D10

Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.

DGND

Digital Ground.

Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.

D0 (LSB)

Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

BYTE

Swaps Pins 6 through 13 with Pins 15 through 22 when HIGH. See Figures 2 and 5.

R/C

With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

enables the parallel output.

Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.

BUSY

At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

have been updated.

ANA

Analog Supply Input. Nominally +5V. Decouple to ground with 0.1

F ceramic and 10

F tantalum capacitors.

DIG

Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be

≤

ANA

DIGITAL

PIN #

NAME

I/O

DESCRIPTION

TABLE I. Pin Assignments.

PIN CONFIGURATION

DIG

ANA

BUSY

R/C

BYTE

D0 (LSB)

AGND1

REF

CAP

AGND2

D15 (MSB)

D14

D13

D12

D11

D10

DGND

ADS7821

CS and R/C are internally OR’d and level triggered. There

is not a requirement which input goes LOW first when

initiating a conversion. If, however, it is critical that CS or

R/C initiates conversion ‘n’, be sure the less critical input is

LOW at least 10ns prior to the initiating input.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. However,

the output will become active whenever R/C goes HIGH.

Refer to the Reading Data section.

BASIC OPERATION

Figure 1 shows a basic circuit to operate the ADS7821 with

a full parallel data output. Taking R/C (pin 24) LOW for a

minimum of 40ns (5

s max) will initiate a conversion.

BUSY (pin 26) will go LOW and stay LOW until the

conversion is completed and the output registers are up-

dated. Data will be output in Straight Binary with the MSB

on pin 6. BUSY going HIGH can be used to latch the data.

All convert commands will be ignored while BUSY is

LOW.

The ADS7821 will begin tracking the input signal at the end

of the conversion. Allowing 10

s between convert com-

mands assures accurate acquisition of a new signal.

STARTING A CONVERSION

The combination of CS (pin 25) and R/C (pin 24) LOW for

a minimum of 40ns immediately puts the sample/hold of the

ADS7821 in the hold state and starts conversion ‘n’. BUSY

(pin 26) will go LOW and stay LOW until conversion ‘n’ is

completed and the internal output register has been updated.

All new convert commands during BUSY LOW will be

ignored. CS and/or R/C must go HIGH before BUSY goes

HIGH or a new conversion will be initiated without suffi-

cient time to acquire a new signal.

The ADS7821 will begin tracking the input signal at the end

of the conversion. Allowing 10

s between convert com-

mands assures accurate acquisition of a new signal. Refer to

Table II for a summary of CS, R/C, and BUSY states and

Figures 3 through 5 for timing diagrams.

R/C

BUSY

OPERATION

None. Databus is in Hi-Z state.

↓

Initiates conversion “n”. Databus remains

in Hi-Z state.

↓

Initiates conversion “n”. Databus enters Hi-Z

state.

↑

Conversion “n” completed. Valid data from

conversion “n” on the databus.

↓

Enables databus with valid data from

conversion “n”.

↓

Enables databus with valid data from

conversion “n-1”

(1)

. Conversion n in progress.

↑

Enables databus with valid data from

conversion “n-1”

(1)

. Conversion “n” in progress.

↑

New conversion initiated without acquisition

of a new signal. Data will be invalid. CS and/or

R/C must be HIGH when BUSY goes HIGH.

New convert commands ignored. Conversion

“n” in progress.

NOTE: (1) See Figures 3 and 4 for constraints on data valid from

conversion “n-1”.

Table II. Control Line Functions for “Read” and “Convert”.

FIGURE 1. Basic Operation.

ADS7821

+5V

0.1µF

10µF

2.2µF

Convert Pulse

40ns min

5µs max

D0 (LSB)

D10

D11

D12

D13

D14

D15 (MSB)

ADS7821

READING DATA

The ADS7821 outputs full or byte-reading parallel data in

Straight Binary data output format. The parallel output will

be active when R/C (pin 24) is HIGH and CS (pin 25) is

LOW. Any other combination of CS and R/C will tri-state

the parallel output. Valid conversion data can be read in a

full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and

pins 15-22. BYTE (pin 23) can be toggled to read both bytes

within one conversion cycle. Refer to Table III for ideal

output codes and Figure 2 for bit locations relative to the

state of BYTE.

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n’ has been initiated, valid data from

conversion ‘n-1’ can be read and will be valid up to 5

s after

the start of conversion ‘n’. Do not attempt to read data from

s after the start of conversion ‘n’ until BUSY (pin 26)

goes HIGH; this may result in reading invalid data. Refer to

Table IV and Figures 3 through 5 for timing specifications.

Note! For the best possible performance, data should not be

read during a conversion. The switching noise of the asyn-

chronous data transfer can cause digital feedthrough degrad-

ing the converter’s performance.

The number of control lines can be reduced by tying CS

LOW while using R/C to initiate conversions and activate

the output mode of the converter. See Figure 3.

DIGITAL OUTPUT

STRAIGHT BINARY

DESCRIPTION

ANALOG INPUT

BINARY CODE

HEX CODE

Full Scale Range

0 to +5V

Least Significant

Bit (LSB)

Full Scale

4.999924V

1111 1111 1111 1111

FFFF

Midscale

2.5V

1000 0000 0000 0000

8000

One LSB below

2.499924V

0111 1111 1111 1111

7FFF

Midscale

Zero Scale

0000 0000 0000 0000

0000

Table III. Ideal Input Voltages and Output Codes.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 26) will go HIGH. Valid data

from conversion ‘n’ will be available on D15-D0 (pin 6-13

and 15-22). BUSY going HIGH can be used to latch the

data. Refer to Table IV and Figures 3 through 5 for timing

specifications.

FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).

Bit 0 (LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 15 (MSB)

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

ADS7821

BYTE LOW

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15 (MSB)

Bit 7

Bit 6

Bit 5