Description
The CXD2408R is an IC developed to generate the
timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
• EIA support
• Electronic shutter function
• Random trigger shutter function
• Sync signal generator
• Supports external synchronization
• Supports non-interlaced operation
• Base oscillation 1560fh (24.5454MHz)
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX074AK, ICX074AL
Absolute Maximum Ratings
• Supply voltage
V
DD
V
SS
– 0.5 to +7.0
V
• Input voltage
V
I
V
SS
– 0.5 to V
DD
+ 0.5 V
• Output voltage
V
O
V
SS
– 0.5 to V
DD
+ 0.5 V
• Operating temperature Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
V
DD
4.75 to 5.25
V
• Operating temperature Topr
–20 to +75
°C
– 1 –
CXD2408R
E94611B68-PS
Timing Generator for Progressive Scan CCD Image Sensor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
– 2 –
CXD2408R
Block Diagram
TG
PULSE GENERATOR
OUTPUT CONTROL
V-CONTROL
V-DECODER
1/525
1/390
H-DECODER
COUNTER
DECODE
1/2
GATE
TEST CIRCUIT
GATE
RG
XH1
XH2
XSHP
XSHD
XRS
XV1
XV2
XV3
XSG
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
CKI
OSCO
OSCI
TRIG
PS
ED0
ED1
ED2
SMD1
SMD2
TEST7
TEST6
TEST5
VRI
HRI
CL
CLD
O2FH
FLD
BLK
SYNC
HDO
VDO
HDI
VDI
EXT
REND
REVH
OCTL
RDM
RM
XCPDM
XCPOB
PBLK
ID
WEN
XSUB
24.5MHz
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
26
27
28
29
30
40
39 38 37 36
35
34
33
41
42
43
44
45
46
47
TEST8
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
1
TEST4
32
TEST3
31
TEST2
21
TEST1
20
NC
– 3 –
CXD2408R
Pin Configuration
TEST4
TEST3
XRS
XSHD
XSHP
XSG
XV1
XV2
V
DD
V
SS
XV3
TEST2
TEST1
XVHOLD
XVOG
XHHG2
CL
CLD
O2FH
NC
FLD
BLK
V
SS
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
OSCO
OSCI
PS
ED0
ED1
ED2
SMD1
V
SS
SMD2
TRIG
RG
XSUB
XH1
XH2
XHHG1A
XHHG1B
TEST8
WEN
ID
PBLK
XCPOB
XCPDM
RM
RDM
V
SS
OCTL
REVH
REND
EXT
TEST7
TEST6
TEST5
CXD2408R (G/A)
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38 37
36 35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
1
– 4 –
CXD2408R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
OSCO
OSCI
PS
ED0
ED1
ED2
SMD1
Vss
SMD2
TRIG
RG
XSUB
XH1
XH2
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
TEST1
TEST2
XV3
Vss
V
DD
XV2
XV1
XSG
XSHP
XSHD
XRS
TEST3
TEST4
TEST5
TEST6
TEST7
O
I
I
I
I
I
I
—
I
I
O
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
I
Inverter output for oscillation.
Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-down resistor)
Low: Parallel input, High: Serial input
Shutter speed setting. Strobe input for serial mode. (With pull-up resistor)
Shutter speed setting. Clock input for serial mode. (With pull-up resistor)
Shutter speed setting. Data input for serial mode. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
GND
Shutter mode setting. (With pull-up resistor)
Trigger input for random trigger shutter.
Reset gate pulse output.
CCD discharge pulse output.
Clock output for CCD horizontal register drive.
Clock output for CCD horizontal register drive.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer from CCD vertical register to CCD horizontal register.
Clock output for adjusting timing of transfer to CCD horizontal register.
Test output. Normally open.
Test output. Normally open.
Clock output for CCD vertical register drive.
GND
Power supply.
Clock output for CCD vertical register drive.
Clock output for CCD vertical register drive.
CCD sensor charge readout pulse output.
Precharge level sample-and-hold pulse.
Data sample-and-hold pulse.
Sample-and-hold pulse.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test input. Set at Low in normal operation. (With pull-down resistor)
Symbol
I/O
Description
– 5 –
CXD2408R
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
EXT
REND
REVH
OCTL
Vss
RDM
RM
XCPDM
XCPOB
PBLK
ID
WEN
TEST8
CL
CLD
O2FH
NC
FLD
BLK
Vss
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
I
I
I
I
—
I
I
O
O
O
O
O
I
O
O
O
—
O
O
—
—
O
I
I
O
O
I
I
I
Internal synchronization/external synchronization switching. (With pull-down resistor)
Low: Internal synchronization, High: External synchronization
Normal reset/direct reset switching. (With pull-down resistor)
Low: Normal reset, High: Direct reset
V reset/HV reset switching. (With pull-down resistor)
Low: V reset, High: HV reset
O2FH output control. (With pull-down resistor)
Low: No output, High: Output
GND
Normal operation/random trigger shutter switching. (With pull-down resistor)
Low: Normal operation, High: Random trigger shutter
Switching for output mode. (With pull-down resistor)
Low: Non-interlaced, High: Interlaced
Clamp pulse output.
Clamp pulse output.
Blanking cleaning pulse output.
Line identification output.
Write enable output.
Test input. (With pull-down resistor)
fck clock output. (0°)
fck clock output. (180°)
2 fH output.
Field pulse output.
Composite blanking output.
GND
Power supply.
Composite sync output.
Horizontal sync signal input.
Vertical sync signal input.
Horizontal sync signal output.
Vertical sync signal output.
Horizontal reset signal input.
Vertical reset signal input.
2 fck clock input.
Symbol
I/O
Description
– 6 –
CXD2408R
Electrical Characteristics
DC Characteristics
(V
DD
= 4.75 to 5.25V, Topr = –20 to +75°C)
Item
Supply voltage
Input voltage 1
(Input pins other than those below)
Input voltage 2
(Pins 7, 9, 10, 58, 59, 62, 63, and 64)
Output voltage 1
(Output pins other than those below)
Output voltage 2 (Pins 28, 29, 30,
31, 32, 33, 34, 49 and 50)
Output voltage 3
(Pins 11, 13, and 14)
Output voltage 4
(Pin 1)
Feedback resistor
Pull-up resistor
Pull-down resistor
Current consumption
V
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
R
FB
R
PU
R
PD
I
DD
I
OH
= –2mA
I
OL
= 4mA
I
OH
= –4mA
I
OL
= 8mA
I
OH
= –12mA
I
OL
= 12mA
I
OH
= –12mA
I
OL
= 12mA
V
IN
= Vss or V
DD
V
IL
= 0V
V
IN
= V
DD
V
DD
= 5V
ICX074AL in normal
operating state
4.75
0.7V
DD
0.7V
DD
–0.8
–0.8
V
DD
– 0.8
V
DD
/2
250k
5.0
1M
50k
50k
35
5.25
0.3V
DD
0.3V
DD
0.4
0.4
0.4
V
DD
/2
2.5M
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
mA
Symbol
Conditions
Min.
Typ.
Max.
Unit
I/O Pin Capacitances
(V
DD
= V
I
= 0V, f
M
= 1MHz)
Item
Input pin capacitance
Output pin capacitance
C
IN
C
OUT
—
—
—
—
9
11
pF
pF
Symbol
Min.
Typ.
Max.
Unit
– 7 –
CXD2408R
AC Characteristics
1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD
CK
XH1
RG
XSHP
XSHD
XRS
CL
CLD
tCK
Vpp/2
0.7V
DD
0.3V
DD
0.3V
DD
0.7V
DD
tpd1
tpd2
tpd3
tpd4
0.3V
DD
tpd5
0.3V
DD
tpd13
0.3V
DD
tpd11
0.3V
DD
tpd9
0.3V
DD
tpd7
0.7V
DD
tpd8
0.7V
DD
tpd6
0.7V
DD
tpd14
0.7V
DD
tpd12
0.7V
DD
tpd10
Symbol
t
CK
t
pd1
t
pd2
t
pd3
t
pd4
t
pd5
t
pd6
t
pd7
t
pd8
t
pd9
t
pd10
t
pd11
t
pd12
t
pd13
t
pd14
CK cycle
XH1 rising delay, activated by the falling edge of CK
XH1 falling delay, activated by the falling edge of CK
RG falling delay, activated by the rising edge of CK
RG rising delay, activated by the falling edge of CK
XSHP falling delay, activated by the rising edge of CK
XSHP rising delay, activated by the falling edge of CK
XSHD falling delay, activated by the rising edge of CK
XSHD rising delay, activated by the falling edge of CK
XRS falling delay, activated by the falling edge of CK
XRS rising delay, activated by the rising edge of CK
CL falling delay, activated by the rising edge of CK
CL rising delay, activated by the rising edge of CK
CLD falling delay, activated by the rising edge of CK
CLD rising delay, activated by the falling edge of CK
41
28
29
27
33
36
30
36
29
34
28
15
17
30
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Definition
Typ.
Unit
(V
DD
= 5.0V, Topr = 25°C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF)
– 8 –
CXD2408R
XH1
RG
0.9V
DD
0.1V
DD
tfH1
trH1
trRG
tfRG
0.9V
DD
0.1V
DD
Symbol
t
rH1
t
fH1
t
rRG
t
fRG
XH1 rise time
XH1 fall time
RG rise time
RG fall time
2
2
2
2
ns
ns
ns
ns
Definition
Typ.
Unit
(V
DD
= 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF)
Waveform Characteristics of XH1 and RG
– 9 –
CXD2408R
VRI
HDO
VDO
VDO
f
H
f
H
L: ODD H: EVEN
tp1
tp2
tp3
tp4
tp5
ODD
EVEN
259H
259H
1
2
2
1
Symbol
t
p1
t
p2
t
p3
t
p4
t
p5
Range of resetting to ODD
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
Prohibited area
21.9
31.6
9.7
200
200
µs
µs
µs
ns
ns
Definition
Specified value
Unit
• In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of
the vertical reset signal as shown in the figure below.
Field identification
– 10 –
CXD2408R
VRI
HDO
VDO
VDO
f
H
f
H
L: ODD H: EVEN
tp1
tp2
tp3
tp4
tp5
ODD
EVEN
1
2
2
1
Symbol
t
p1
t
p2
t
p3
∗
t
p4
t
p5
Range of resetting to ODD
Range of resetting to EVEN
Range of resetting to ODD
Prohibited area
Prohibited area
21.9
31.6
—
200
200
µs
µs
µs
ns
ns
Definition
Specified value
Unit
• In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the
vertical reset signal as shown in the figure below.
Field identification
∗
In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified.
– 11 –
CXD2408R
Description of Operation
1. Mode Control
Symbol
RM
RDM
PS
EXT
REND
REVH
42
41
3
36
37
38
1/30s non-interlaced
Normal operation
Parallel
Internal synchronization
Normal reset
V reset
1/60s interlaced
Random trigger shutter
Serial
External synchronization
Direct reset
HV reset
Electronic shutter speed input method
Pin No.
L
H
Remarks
2. Mode Relationships
RM
L
1/30s non-interlaced
L
Internal synchronization
L
H
Normal
operation
Random
trigger
shutter
Normal operation
H
Direct reset
L
Normal
reset
External synchronization
H
H
1/60s interlaced
L
Internal synchronization
L
H
Normal
operation
Random
trigger
shutter
Normal operation
L
V
reset
H
HV
reset
External synchronization
H
EXT
RDM
REND
REVH
: Disabled
Direct reset
L
H
V
reset
HV
reset
– 12 –
CXD2408R
3. Electronic Shutter
<Shutter Modes>
SMD1
SMD2
L
L
Flickerless: Eliminates fluorescent frequency-induced flicker.
L
H
High-speed shutter: Shutter speed faster than 1/60
H
L
Low-speed shutter: Shutter speed slower than 1/60
H
H
No shutter operation
<Shutter Mode and Speed Setting Method>
PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2.
PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin.
3-1. Parallel input
Shutter Speed Compatibility Chart
Mode
OFF
Flickerless
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H