3000-pixel CCD Linear Image Sensor (B/W)
Description
The ILX103A is a rectangular reduction type CCD
linear image sensor designed for bar code POS
hand scanner and optical measuring equipment use.
A built-in timing generator and clock-drivers ensure
single 5V power supply for easy use.
Features
• Number of effective pixels: 3000 pixels
• Pixel size: 7µm
×
200µm (7µm pitch)
• S/H output
• Built-in timing generator and clock-drivers
• Output amplifier gain switching function
(2-level: switching gain ratio 1:4)
• SIP small package
• Clock frequency: 500kHz (Typ.),
100kHz (Min.), 1MHz (Max.)
Absolute Maximum Ratings
• Supply voltage
V
DD
6
V
• Operating temperature
–10 to +60
°C
• Storage temperature
–30 to +80
°C
Pin Configuration (Top View)
Internal Structure
– 1 –
E98X48A91-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ILX103A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
V
DD
GND
V
out
Vgg
φ
CLK
SWG
NC
NC
φ
RO
G
φ
SHUT
GND
V
DD
T1
V
DD
GND
NC
3000
Vgg
GND
V
DD
V
DD
GND
V
DD
GND
D24
D25
D54
D55
S1
S2
S3
S2999
S3000
D56
D65
Output Amplifier
Driver
Readout gate
Readout gate
CCD analog shift register
CCD analog shift register
Driver
Readout gate pulse
generator
Shutter pulse
generator
T
iming generator
4
2
1
12
11
14
15
6
13
5
9
10
φ
SHUT
φ
ROG
φ
CLK
T1
SWG
V
out
3
16 pin SIP (Ceramic)
– 2 –
ILX103A
Pin Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
DD
GND
Vout
Vgg
φ
CLK
SWG
NC
NC
φ
ROG
φ
SHUT
GND
V
DD
T1
V
DD
GND
NC
Power supply
GND
Signal output
Output circuit gate bias
Clock pulse input
Control (Output circuit amplification factor
×
4/
×
1)
NC
NC
Readout gate pulse input
Electrical shutter pulse input
GND
Power supply
TEST (Connect to GND with 1000pF capacitor)
Power supply
GND
NC
Recommended Voltage
Item
V
DD
Min.
4.5
Mode Description
Output circuit gain
High
Low
Pin 6 SWG
V
DD
GND
Typ.
5.0
Max.
5.5
Unit
V
Input Pin Capacity
Symbol
C
φ
CLK
C
φ
ROG
C
φ
SHUT
Min.
—
—
—
Typ.
10
10
10
Max.
—
—
—
Unit
pF
pF
pF
Item
Input capacity of
φ
CLK pin
Input capacity of
φ
ROG pin
Input capacity of
φ
SHUT pin
– 3 –
ILX103A
Electro-optical Characteristics (Analog Characteristic) (Note 1)
Ta = 25°C, V
DD
= 5V, Clock frequency: 500kHz, Light source = 3200K,
IR cut filter: CM-500S (t = 1.0mm), Output circuit gain low mode
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
5V current consumption
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
V
SAT
V
DRK
DSNU
IL
DR
SE
I
VDD
TTE
Z
O
V
OS
52.5
—
—
0.6
—
—
—
—
—
—
92.0
—
—
75
925
5.0
0.8
2.5
5.0
5.0
320
0.01
7.0
97.0
250
2.5
97.5
—
10.0
—
6.0
12.0
—
—
—
17.0
—
—
—
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
%
Ω
V
Note 2
Note 3
Note 4
—
Note 5
Note 6
Note 7
Note 8
Note 9
—
—
—
Note 10
Note)
1. In accordance with the given electro-optical characteristics, the even black level is defined as the average
value of D24, D25 to D53.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. Light source: LED
λ
= 660nm
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
PRNU =
×
100 [%]
The maximum output of the effective pixels is set to V
MAX
, the minimum output to V
MIN
and the average
output to V
AVE
.
5. Integration time is 10ms.
6. The difference between the maximum and average values and the difference between the minimum and
average values of the dark output voltage is calculated. The larger value is defined as dark signal
nonuniformity. Integration time is 10ms.
7. Typical value is used for clock pulse and readout pulse. V
OUT
= 500mV.
8. DR = V
SAT
/V
DRK
When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in
proportion to optical integration time.
9. SE = V
SAT
/R1
10. Vos is defined as indicated below.
(V
MAX
– V
MIN
)/2
V
AVE
D51
D52
Vout
V
OS
GND
D53
D54
D55
S1
– 4 –
ILX103A
–1
D1
D0
5
0
5
0
5
φ
R
O
G
φ
S
H
U
T
φ
C
L
K
V
O
U
T
O
p
ti
c
a
l
b
la
c
k
(3
0
p
ix
e
ls
)
D
u
m
m
y
s
ig
n
a
l
(5
5
p
ix
e
ls
)
1
-L
in
e
o
u
tp
u
t
p
e
ri
o
d
(
3
0
6
6
p
ix
e
ls
)
3
1
0
0
o
r
m
o
re
c
lo
c
k
p
u
ls
e
s
a
re
r
e
q
u
ir
e
d
.
E
ff
e
c
ti
v
e
p
ic
tu
re
e
le
m
e
n
ts
s
ig
n
a
l
(3
0
0
0
p
ix
e
ls
)
D
u
m
m
y
s
ig
n
a
l
(1
0
p
ix
e
ls
)
0
D2
D3
D4
D2
1
D2
2
D2
3
D2
4
0
1
2
D5
3
D5
4
D5
5
S1
S2
S3
S4
S2
99
8
S2
99
7
S2
99
9
S3
00
0
D5
6
D5
7
D5
8
D5
9
D6
1
D6
0
D6
2
D6
3
D6
4
D6
5
Clock Timing Diagram
– 5 –
ILX103A
Input Clock Voltage Condition
Min.
3.0
0.0
Typ.
V
DD
—
Max.
5.5
0.1
Unit
V
V
Item
V
IH
V
IL
Symbol
t
1,
t
2
—
Min.
0
40
Typ.
10
50
Max.
100
60
Unit
ns
%
Item
φ
CLK pulse rise/fall time
φ
CLK pulse Duty
∗
1
Symbol
t
5
t
9
t
6,
t
8
t
7
Min.
1/8
τ
1/8
τ
0
6
τ
Typ.
1/4
τ
1/4
τ
10
10
τ
Max.
3/8
τ
3/8
τ
100
20
τ
Unit
ns
ns
ns
ns
Item
φ
ROG,
φ
CLK pulse timing 1
φ
ROG,
φ
CLK pulse timing 2
φ
ROG pulse rise/fall time
φ
ROG pulse period
∗
This is applied to the all external pulses.
(
φ
CLK,
φ
ROG,
φ
SHUT)
φ
CLK Timing (For all modes)
t1
t3
t4
t2
φ
CLK
∗
1
100
×
t
4/ (
t
3 +
t
4)
φ
ROG,
φ
CLK Timing
t6
t7
t8
φ
ROG
φ
CLK
t9
t5
Note)
τ
is the period of
φ
CLK.
– 6 –
ILX103A
φ
SHUT,
φ
CLK Timing
Symbol
t
11,
t
13
t
12
t
14
t
15
Min.
0
4000
150
150
Typ.
10
5000
200
200
Max.
100
—
250
250
Unit
ns
ns
ns
ns
Item
φ
SHUT pulse rise/fall time
φ
SHUT pulse period
φ
SHUT,
φ
CLK pulse timing 1
φ
SHUT,
φ
CLK pulse timing 2
φ
SHUT
φ
CLK
t11
t12
t13
t15
t14
Symbol
t
16
Min.
—
Typ.
230
Max.
—
Unit
ns
Item
φ
CLK-Vout output delay time1
φ
CLK
Vout
t16
∗
2
∗
1
fck = 500kHz,
φ
CLK Duty = 50%,
φ
CLK rise/fall time = 10ns
∗
2
is data period.
φ
CLK Output Signal Timing
∗
1
Note) The high periods of
φ
ROG and
φ
SHUT are separated for 10
τ
or more.
– 7 –
ILX103A
Application Circuit (Output gain low mode)
∗
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
V
D
D
3k
Ω
1
µ
/16V
0.01
µ
1000p
22
µ
/10V
φ
CLK
φ
ROG
φ
SHUT
5V
2SA1175
Signal output
G
N
D
V
o
u
t
V
g
g
φ
C
L
K
S
W
G
N
C
N
C
φ
R
O
G
φ
S
H
U
T
G
N
D
V
D
D
T
1
V
D
D
G
N
D
N
C
∗
2
∗
1
This circuit diagram is the case when output circuit gain is low.
∗
2
Connect T1 (Pin 13) to GND with 1000pF capacitor.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 8 –
ILX103A
Example of Representative Characteristics (V
DD
= 5V, Ta = 25°C)
10
9
8
7
6
5
4
3
2
1
0
400
500
600
700
Wavelength [nm]
Spectral sensitivity characteristics (Standard characteristics)
R
e
la
ti
v
e
s
e
n
s
it
iv
it
y
800
900
1000
10
5
1
0.5
0.1
0.05
0.01
–10
0
10
20
Ta – Ambient temperature [
°
C]
Output voltage vs. Temperature characteristics (Standard characteristics)
O
u
tp
u
t
v
o
lt
a
g
e
r
a
te
30
40
50
60
– 9 –
ILX103A
5
4
3
2
1
0
–10
0
10
20
Ta – Ambient temperature [
°
C]
Offset level vs. Temperature characteristics
(Standard characteristics)
V
O
S
–
O
ff
s
e
t
le
v
e
l
[V
]
30
40
50
60
∆
Vos
∆
Ta
~
– –2.1mV/
°
C
5
4
3
2
1
0
4.5
V
DD
[V]
Offset level vs. V
DD
characteristics
(Standard characteristics)
V
O
S
–
O
ff
s
e
t
le
v
e
l
[V
]
5
5.5
∆
Vos
∆
V
DD
~
– 0.49
Ta = 25
°
C
14
10
12
8
6
4
2
0
4.5
5
V
DD
[V]
Supply current vs. V
DD
characteristics
(Standard characteristics)
I
V
D
D
–
S
u
p
p
ly
c
u
rr
e
n
t
[m
A
]
5.5
Ta = 25
°
C
10
5
1
10
τ
– Integration time [ms]
Output voltage vs. Integration time
(Standard characteristics)
O
u
tp
u
t
v
o
lt
a
g
e
r
a
te
50
100
– 10 –
ILX103A
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-SIP Packages
The following points should be observed when handling and installing cer-SIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1) Compressive strength: 39N/surface (Do not apply load more than 0.5mm inside the outer perimeter of
the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with a soldering iron.
(3) Rapid cooling or heating.
(4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
Upper ceramic layer
39N
Lower ceramic layer
Low-melting glass
(1)
29N
(3)
0.9Nm
(4)
29N
(2)
– 11 –
ILX103A
4) Dust and dirt protection
a) Operate in clean environments.