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– 1 –
CXA2074Q/S
E96843B86
US Audio Multiplexing Decoder
Description
The CXA2074Q/S is an IC designed as a decoder
for the Zenith TV Multi-channel System and also
corresponds with I
2
C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I
2
C BUS.
Features
• Audio multiplexing decoder, dbx noise reduction
decoder and sound processor are all included in a
single chip. Almost any sort of signal processing is
possible through this IC.
• All adjustments are possible through I
2
C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There are three systems for inputs and two
systems for outputs, and each mode control is
possible.
Standard I/O Level
[( ) is the pin No. for the CXA2074S.]
• Input level
COMPIN (Pin 17)
245mVrms
AUX1-L/R (Pins 36 and 35)
490mVrms
AUX2-L/R (Pins 38 and 37)
490mVrms
• Output level
LPOUT-L/R (Pins 40 and 39)
490mVrms
LSOUT-L/R (Pins 8 and 7)
490mVrms
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
V
CC
11
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation
P
D
0.6 (48 pin QFP) W
2.2 (42 pin SDIP) W
Range of Operating Supply Voltage
9 ± 0.5
V
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
∗
A license of the dbx-TV noise reduction system is
required for the use of this device.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA2074Q
48 pin QFP (Plastic)
CXA2074S
42 pin SDIP (Plastic)
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– 2 –
CXA2074Q/S
A
U
X
1
-L
A
U
X
1
-R
V
C
A
W
G
T
V
C
A
T
C
V
C
A
IN
V
E
O
U
T
V
E
W
G
T
V
E
S
A
P
IN
S
A
P
O
U
T
S
T
IN
S
U
B
O
U
T
V
C
C
V
E
T
C
N
O
IS
E
T
C
T
R
E
R
T
R
E
L
S
D
A
S
C
L
D
G
N
D
M
A
IN
IN
M
A
IN
O
U
T
P
C
IN
T
2
P
L
IN
T
C
O
M
P
IN
V
G
R
IR
E
F
G
N
D
S
A
P
T
C
P
C
IN
T
1
B
A
S
S
R
1
B
A
S
S
R
2
B
A
S
S
L
1
B
A
S
S
L
2
L
S
O
U
T
-R
L
S
O
U
T
-L
L
P
IN
-L
L
P
IN
-R
L
P
O
U
T
-L
A
U
X
2
-L
A
U
X
2
-R
L
P
O
U
T
-R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Configuration (Top View)
CXA2074Q
CXA2074S
25
26
27
28
29
30
36 35
34
31
32
33
A
U
X
1
-L
A
U
X
1
-R
N
C
V
C
A
W
G
T
V
C
A
T
C
V
C
A
IN
V
E
O
U
T
N
C
V
E
T
C
V
E
W
G
T
V
E
S
A
P
IN
2
3
4
5
6
7
8
9
10
11 12
1
T
R
E
L
L
S
O
U
T
-R
L
S
O
U
T
-L
S
C
L
D
G
N
D
N
C
P
C
IN
T
2
N
C
M
A
IN
O
U
T
M
A
IN
IN
S
D
A
P
C
IN
T
1
13
14
15
16
17
18
19
20
21
22
23
24
PLINT
COMPIN
IREF
GND
SAPTC
NC
STIN
NOISETC
VGR
V
CC
SAPOUT
SUBOUT
40
39
38
37
41
42
43
44
45
46
47
48
TRER
BASSL2
BASSL1
BASSR2
LPOUT-L
BASSR1
LPIN-L
LPIN-R
LPOUT-R
AUX2-L
AUX2-R
NC
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– 3 –
CXA2074Q/S
Block Diagram
CXA2074Q
VG
R
IR
EF
DG
ND
SC
L
SD
A
SA
PO
UT
SA
PIN
ST
IN
VE
VE
WG
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VE
TC
VE
OU
T
VC
AIN
VC
AW
GT
VC
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C
MA
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LS
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LS
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M2
TR
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TR
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BA
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1
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3
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2
3
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1
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1
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3
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5
1
6
6
5
4
2
4
2
5
2
2
PS
W
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VG
R
IR
EF
DG
ND
SC
L
SD
A
SA
PO
UT
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PIN
ST
IN
VE
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(+
6
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)
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LS
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M2
TR
EB
LE
TR
EB
TR
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BA
SS
BA
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BA
SS
AU
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A
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2
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B
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2
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1
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(+
4
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I
2
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IN
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L
P
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L
P
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F
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T
2
FE