– 1 –
ICX039DNA
E95Y14C99
Diagonal 8mm (Type 1/2) CCD Image Sensor for PAL Color Video Cameras
Description
The ICX039DNA is an interline CCD solid-state
image sensor suitable for PAL color video cameras
with a diagonal 8mm (Type 1/2) system. Smear,
sensitivity, D-range, S/N and other characteristics
have been greatly improved compared with the
ICX039BNA. High sensitivity and low dark current
are achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filters and HAD
(Hole-Accumulation Diode) sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
This chip is compatible with and can replace the
ICX039BNA.
Features
• Low smear (–20dB compared with the ICX039BNA)
• High sensitivity (+3.0dB compared with the ICX039BNA)
• High D range (+2.5dB compared with the ICX039BNA)
• High S/N
• High resolution and low dark current
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Continuous variable-speed shutter
• Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register:
5V drive
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 8mm (Type 1/2)
• Number of effective pixels: 752 (H) x 582 (V) approx. 440K pixels
• Total number of pixels:
795 (H) x 596 (V) approx. 470K pixels
• Chip size:
7.95mm (H) x 6.45mm (V)
• Unit cell size:
8.6µm (H) x 8.3µm (V)
• Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction
: Front 12 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
• Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
20 pin DIP (Cer-DIP)
Pin 1
V
3
40
2
12
Pin 11
H
Optical black position
(Top View)
– 2 –
ICX039DNA
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
9
10
V
φ
4
V
φ
3
V
φ
2
φ
SUB
GND
V
φ
1
V
L
GND
V
DD
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
GND
Vertical register transfer clock
Protective transistor bias
GND
Output circuit supply voltage
Signal output
11
12
13
14
15
16
17
18
19
20
V
GG
V
DSUB
V
SS
GND
GND
RD
φ
RG
NC
H
φ
1
H
φ
2
Output circuit gate bias
Substrate bias circuit supply voltage
Output circuit source
GND
GND
Reset drain bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note)
Note) : Photo sensor
G
N
D
V
L
V
φ
1
G
N
D
φ
S
U
B
V
φ
2
V
φ
3
V
φ
4
V
G
G
V
D
S
U
B
V
S
S
G
N
D
G
N
D
R
D
φ
R
G
N
C
Horizontal Register
17
18
19
20
V
D
D
V
O
U
T
H
φ
1
H
φ
2
Cy
Mg
Cy
G
Cy
Mg
Ye
G
Ye
Mg
Ye
G
Cy
Mg
Cy
G
Cy
Mg
Ye
G
Ye
Mg
Ye
G
V
e
rt
ic
a
l
R
e
g
is
te
r
Block Diagram and Pin Configuration
(Top View)
Pin Description
– 3 –
ICX039DNA
Item
–0.3 to +50
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Ratings
Unit
Remarks
Absolute Maximum Ratings
∗
1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Substrate clock
φ
SUB
– GND
V
DD
, V
RD
, V
DSUB
, V
OUT
, V
SS
– GND
Supply voltage
V
DD
, V
RD
, V
DSUB
, V
OUT
, V
SS
–
φ
SUB
V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4
– GND
Clock input voltage
V
φ
1
, V
φ
2
, V
φ
3
, V
φ
4
–
φ
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
φ
1
, H
φ
2
– V
φ
4
φ
RG
, V
GG
– GND
φ
RG
, V
GG
–
φ
SUB
V
L
–
φ
SUB
Pins other than GND and
φ
SUB
– V
L
Storage temperature
Operating temperature
– 4 –
ICX039DNA
Item
V
DD
V
RD
V
GG
V
SS
V
L
V
DSUB
V
SUB
∆
V
SUB
14.55
14.55
1.75
6.0
–3
15.0
15.0
2.0
∗
3
∗
4
15.45
15.45
2.25
14.0
+3
V
V
V
V
%
V
RD
= V
DD
∗
5
∗
5
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
∗
3
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
∗
4
Connect to GND or leave open.
∗
5
The setting value of the substrate voltage (V
SUB
) is indicated on the back of the image sensor by a special
code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
V
SUB
code — one character indication
Code and optimal setting correspond to each other as follows.
DC Characteristics
Item
Output circuit supply current
I
DD
5.0
10.0
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
V
SUB
code
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
<Example> "L"
→
V
SUB
= 9.0V
Item
V
DD
V
RD
V
GG
V
SS
V
L
V
DSUB
φ
SUB
14.55
14.55
1.75
14.55
15.0
15.0
2.0
∗
1
15.0
∗
2
15.45
15.45
2.25
15.45
V
V
V
V
V
RD
= V
DD
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
Grounded with 390
Ω
resistor
∗
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
∗
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Grounded with 390
Ω
resistor
– 5 –
ICX039DNA
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
φ
V
| V
VH1
– V
VH2
|
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
φ
H
V
HL
V
RGL
V
φ
RG
V
RGLH
– V
RGLL
V
φ
SUB
14.55
–0.05
–0.2
–9.6
8.3
–0.25
–0.25
4.75
–0.05
4.5
23.0
15.0
0
0
–9.0
9.0
5.0
0
∗
1
5.0
24.0
15.45
0.05
0.05
–8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
φ
V
= V
VH
n – V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
∗
1
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ. Max. Unit
Waveform
diagram
Remarks
Item
Symbol
Min.
Typ. Max. Unit
Waveform
diagram
Remarks
∗
1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Reset gate clock
voltage
V
RGL
V
φ
RG
–0.2
8.5
0
9.0
0.2
9.5
V
Vp-p
4
4
Clock Voltage Conditions
– 6 –
ICX039DNA
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock
and GND
C
φ
V1
, C
φ
V3
C
φ
V2
, C
φ
V4
C
φ
V12
, C
φ
V34
C
φ
V23
, C
φ
V41
C
φ
H1
C
φ
H2
C
φ
HH
C
φ
RG
C
φ
SUB
R
1
, R
2
, R
3
, R
4
R
GND
1800
2200
450
270
64
62
47
8
400
68
15
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Symbol
Min.
Typ.
Max.
Unit Remarks
H
φ
2
H
φ
1
C
φ
H1
C
φ
H2
C
φ
HH
V
φ
1
C
φ
V12
V
φ
2
V
φ
4
V
φ
3
C
φ
V34
C
φ
V23
C
φ
V41
C
φ
V1
C
φ
V2
C
φ
V4
C
φ
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
– 7 –
ICX039DNA
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
φ
M
0V
φ
M
2
V
φ
1
V
φ
3
V
φ
2
V
φ
4
V
VHH
V
VH
V
VHL
V
VHH
V
VHL
V
VH1
V
VL1
V
VLH
V
VLL
V
VL
V
VHH
V
VH3
V
VHL
V
VH
V
VHH
V
VHL
V
VL3
V
VL
V
VLL
V
VLH
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VHH
V
VHL
V
VH4
V
VHL
V
VH
V
VL
V
VLH
V
VLL
V
VL4
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
φ
V
= V
VH
n – V
VL
n (n = 1 to 4)
– 8 –
ICX039DNA
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
twl
V
φ
H
V
HL
(4) Reset gate clock waveform
Point A
twl
V
φ
RG
V
RGH
V
RGL
+ 0.5V
V
RGL
+2.5V
V
RGLH
RG waveform
V
RGLL
H
φ
1
waveform
twh
tr
tf
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of V
RGLH
and
V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
)/2
Assuming V
RGH
is the minimum value during the period twh, then:
V
φ
RG
= V
RGH
– V
RGL
– 9 –
ICX039DNA
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
φ
M
φ
M
2
V
φ
SUB
Clock Switching Characteristics
Item
Readout clock
Vertical transfer
clock
During
imaging
During parallel-
serial
conversion
Reset gate clock
Substrate clock
V
T
V
φ
1
, V
φ
2
,
V
φ
3
, V
φ
4
H
φ
H
φ
1
H
φ
2
φ
RG
φ
SUB
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
0.5
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
µs
ns
ns
µs
ns
µs
During
readout