CMOS 8-bit Single Chip Microcomputer
Description
The CXP86609/86613/86617 are the CMOS 8-bit
single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time-base timer, I
2
C bus interface, PWM output,
remote control reception circuit, watchdog timer,
32kHz timer/counter besides the basic configurations
of 8-bit CPU, ROM, RAM, I/O ports.
The CXP86609/86613/86617 also provide a sleep
function that enables to lower the power consumption.
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM
8K bytes (CXP86609)
12K bytes (CXP86613)
16K bytes (CXP86617)
• Incorporated RAM
352 bytes
• Peripheral functions
— A/D converter
8 bits, 6 channels, successive approximation method
(Conversion time of 3.25µs at 16MHz)
— Serial interface
8-bit clock sync type, 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
32kHz timer/counter
— I
2
C bus interface
— PWM output
8 bits, 4 channels
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Watchdog timer
• Interruption
11 factors, 11 vectors, multi-interruption possible
• Standby mode
Sleep
• Package
52-pin plastic SDIP
• Piggyback/evaluator
CXP86490 64-pin ceramic PSDIP
Perchase of Sony's I
2
C components conveys a licence under the Philips I
2
C Patent Rights to use these components
in an I
2
C system, provided that the system conforms to the I
2
C Standard Specifications as defined by Philips.
– 1 –
E97751-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP86609/86613/86617
52 pin SDIP (Plastic)
Structure
Silicon gate CMOS IC
– 2 –
CXP86609/86613/86617
A
/D
C
O
N
V
E
R
T
E
R
F
IF
O
R
E
M
O
C
O
N
S
E
R
IA
L
I
N
T
E
R
F
A
C
E
U
N
IT
8
B
IT
T
IM
E
R
1
8
B
IT
T
IM
E
R
/
C
O
U
N
T
E
R
0
I
2
C
B
U
S
IN
T
E
R
F
A
C
E
U
N
IT
8
B
IT
P
W
M
P
R
E
S
C
A
L
E
R
/
T
IM
E
B
A
S
E
T
IM
E
R
W
A
T
C
H
D
O
G
T
IM
E
R
3
2
k
H
z
T
IM
E
R
/C
O
U
N
T
E
R
R
O
M
8
K
/1
2
K
/1
6
K
B
Y
T
E
S
R
A
M
3
5
2
B
Y
T
E
S
S
P
C
7
0
0
C
P
U
C
O
R
E
C
L
O
C
K
G
E
N
E
R
A
T
O
R
/S
Y
S
T
E
M
C
O
N
T
R
O
L
IN
TE
RR
UP
T C
ON
TR
OL
LE
R
PO
RT
A
PO
RT
G
P
G
7
1
PO
RT
E
P
E
4
t
o
P
E
6
3
P
E
2
t
o
P
E
3
2
P
E
0
t
o
P
E
1
2
PO
RT
D
P
D
0
t
o
P
D
7
8
PO
RT
B
P
B
0
t
o
P
B
7
8
P
A
0
t
o
P
A
7
8
PW
M0
to
P
WM
3
AD
J
SC
L1
SC
L0
SD
A1
SD
A0
T
O
E
C
S
C
K
S
O
S
I
R
M
C
A
N
0
t
o
A
N
5
6
2
2
IN
T0
IN
T1
IN
T2
TE
X
TX
EX
TA
L
XT
AL
RS
T
V
DD
V
SS
4
PO
RT
F
P
F
0
t
o
P
F
3
4
P
F
4
t
o
P
F
7
4
Block Diagram
– 3 –
CXP86609/86613/86617
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
31
32
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
V
SS
V
DD
NC
NC
NC
PE4
PE5
PE6
NC
NC
NC
PB0
PB1
PB2
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO/ADJ
PE1
PE2/TEX/INT0
PE3/TX
PD4
PD7/EC
PD6/RMC
PD5
PD3/SI
PD2/SO
PD1/SCK
PD0/INT2
PA7
PA6
RST
V
SS
PA0/AN0
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PB7
PB6
PB5
PB4
PB3
PG7/INT1
Pin Assignment (Top View)
Note) 1. NC (Pins 30, 31, 32, 36 and 38) are left open.
2. Vss (Pins 12 and 40) are both connected to GND.
3. Pin 37 is the NC pin. However, connect it to V
DD
because it is the
EXLC pin (input) for the piggyback/evaluator and OTP devices.
– 4 –
CXP86609/86613/86617
(Port A)
8-bit I/O port.
I/O can be set in
a unit of single bits.
(8 pins)
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port D)
8-bit I/O port.
I/O can be set in
a unit of single bits.
Can drive 12mA
sink current.
(8 pins)
(Port E)
Bits 0 and 1 are
I/O port; I/O can
be set in a unit of
single. Bits 2 and 3
are input port.
Bits 4, 5 and 6 are
output port.
(7 pins)
Pin Description
Symbol
PA0/AN0
to
PA5/AN5
PA6 to PA7
PB0 to PB7
PD0/INT2
PD1/SCK
PD2/SO
PD3/SI
PD4 to PD5
PD6/RMC
PD7/EC
PE0/TO/ADJ
PE1
PE2/TEX/INT0
PE3/TX
PE4 to PE6
I/O/
Analog input
I/O
I/O
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O
I/O/Input
I/O/Input
I/O/Output/
Output
I/O
Input/Input/
Input
Input/Output
Output
I/O
Description
Analog inputs to A/D converter.
(6 pins)
External interruption request input.
Active at the falling edge.
Serial clock I/O.
Serial data output.
Serial data input.
Remote control reception circuit input.
External event input for timer/counter.
Rectangular wave output
for 8-bit timer/counter.
Connects a crystal for
32kHz timer/counter
clock oscillation.
When used as an event
counter, input to TEX pin
and leave TX pin open.
32kHz oscillation
frequency dividing output.
External interruption
request input. Active at
the falling edge.
– 5 –
CXP86609/86613/86617
(Port F)
8-bit output port and
large current (12mA)
N-channel open
drain output. Lower
4 bits are medium
voltage drive (12V);
upper 4 bits are 5V
drive.
(8 pins)
(Port G)
1-bit I/O port. I/O can be set in a unit
of single bits.
(1 pin)
Connects a crystal for system clock oscillation. When a clock is
supplied externally, input to EXTAL pin and input a reversed phase
clock to XTAL pin.
System reset; active at Low level.
No connected. Connect this pin to V
DD
under normal operation.
Positive power supply.
GND. Connect two Vss pins to GND.
8-bit PWM output.
(4 pins)
Symbol
PF0/PWM0 to
PF3/PWM3
PG7/INT1
RST
NC
V
DD
Vss
Output/Output
I/O/Input
Input
I/O
Description
External interruption request
input. Active at the falling edge.
PF4/SCL0 to
PF5/SCL1
PF6/SDA0 to
PF7/SDA1
Output/I/O
Output/I/O
I
2
C bus interface transfer clock I/O.
(2 pins)
I
2
C bus interface transfer data I/O.
(2 pins)
EXTAL
XTAL
Input
Output
– 6 –
CXP86609/86613/86617
Port A data
Port A direction
IP
RD (Port A)
Data bus
"0" after reset
Port A function selection
"0" after reset
A/D converter
Input multiplexer
Input protection
circuit
Port A data
Port A direction
IP
RD (Port A)
Data bus
"0" after reset
Schmitt input
Ports B, G data
Ports B, G direction
IP
RD (Ports B, G)
Data bus
INT1
"0" after reset
Schmitt input
only for PG7
Input/Output Circuit Formats for Pins
Port A
Port A
Port B
Port G
6 pins
2 pins
9 pins
Hi-Z
Hi-Z
Hi-Z
Pin
After reset
Circuit format
PA6
PA7
PA0/AN0
to
PA5/AN5
PB0 to PB7
PG7/INT1
– 7 –
CXP86609/86613/86617
Port D data
Port D direction
IP
RD (Port D)
Data bus
INT2, SI,
RMC, EC
"0" after reset
Schmitt input
∗
Large current 12mA
∗
Port D data
Port D direction
IP
RD (Port D)
Data bus
"0" after reset
Schmitt input
only for PD1
SCK, SO
SIO output enable
SCK only
∗
Large current 12mA
∗
Port D
Port D
4 pins
2 pins
Hi-Z
Hi-Z
PD1/SCK
PD2/SO
PD0/INT2
PD3/SI
PD6/RMC
PD7/EC
Port D data
Port D direction
IP
RD (Port D)
Data bus
"0" after reset
Schmitt input
∗
Large current 12mA
∗
Port D
2 pins
PD4
PD5
Hi-Z
Pin
After reset
Circuit format
– 8 –
CXP86609/86613/86617
IP
IP
32kHz oscillation circuit control
RD (Port E)
Schmitt input
Schmitt input
Clock input
Data bus
Data bus
INT0
"1" after reset
PE2/
TEX/
INT0
PE3/
TX
RD (Port E)
Port E data
Port E direction
IP
RD (Port E)
Data bus
"1" after reset
"1" after reset
Port E
Port E
1 pin
2 pins
PE2/TEX/INT0
PE3/TX
High level
Oscillation
stop
Port input
PE1
Port E data
"1" after reset
TO
ADJ16K
ADJ2K
∗
1
∗
1
01
00
10
11
MPX
Data bus
Port E direction
"1" after reset
Port E function selection (lower)
"00" after reset
IP
Port E function selection (upper)
Internal reset signal
∗
2
∗
1
ADJ signals are frequency
dividing outputs for 32kHz
oscillation frequency
adjustment.
ADJ2K provides usage as
buzzer output.
∗
2
Pull-up transistor approx. 150k
Ω
RD (Port E)
Port E
1 pin
High level
(with the
resistor of
pull-up
transistor ON
when reset)
PE0/TO/ADJ
Pin
After reset
Circuit format
– 9 –
CXP86609/86613/86617
4 pins
Hi-Z
I
2
C output enable
Port F data
"1" after reset
SCL, SDA
SCL, SDA
(I
2
C circuit)
IP
Schmitt input
∗
Large current 12mA
To internal I
2
C pins
(SCL1 for SCL0)
BUS SW
∗
Port F
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
IP
EXTAL
XTAL
• Diagram shows the circuit
composition during oscillation.
• Feedback resistor is removed
during stop.
(This device does not enter the
stop mode.)
Schmitt input
Pull-up resistor
OP
Mask option
2 pins
EXTAL
XTAL
1 pin
RST
Oscillation
Low level
(when reset)
3 pins
Hi-Z
PE4
PE5
PE6
Port E data
Output becomes active from
high impedance by data writing
to port register.
Data bus
RD (Port E)
Port E
Port F data
Port F function selection
"0" after reset
"1" after reset
PWM0 to PWM3
∗
12V drive
Large current 12mA
∗
RD (Port F)
Data bus
Port F
4 pins
PF0/PWM0
to
PF3/PWM3
Hi-Z
Pin
After reset
Circuit format
– 10 –
CXP86609/86613/86617
∗
1
V
IN
and V
OUT
should not exceed V
DD
+ 0.3V.
∗
2
The large current output port is Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.
V
DD
V
IN
V
OUT
V
OUTP
I
OH
∑
I
OH
I
OL
I
OLC
∑
I
OL
Topr
Tstg
P
D
–0.3 to +7.0
–0.3 to +7.0
∗
1
–0.3 to +7.0
∗
1
–0.3 to +15.0
–5
–50
15
20
130
–20 to +75
–55 to +150
375
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Total of all output pins
Ports excluding large current output (value per pin)
Large current output ports (value per pin
∗
2
)
Total of all output pins
SDIP-52P-01
Item
Symbol
Ratings
Unit
Remarks
Absolute Maximum Ratings
(Vss = 0V reference)
Supply voltage
High level input voltage
Low level input voltage
Operating temperature
5.5
5.5
5.5
—
V
DD
V
DD
V
DD
+ 0.3
0.3V
DD
0.2V
DD
0.4
+75
V
V
V
V
V
V
V
V
V
V
°C
Item
Symbol
Min.
Max.
Unit
Remarks
4.5
3.5
2.7
—
0.7V
DD
0.8V
DD
V
DD
– 0.4
0
0
–0.3
–20
V
IH
V
IHS
V
IHEX
V
IL
V
ILS
V
ILEX
Topr
Guaranteed operation range for 1/2 and 1/4
frequency dividing clocks
Guaranteed operation range for 1/16
frequency dividing clock or sleep mode
Guaranteed operation range for TEX
Guaranteed data hold range for stop
∗
1
∗
2
∗
3
EXTAL pin
∗
4
, TEX pin
∗
5
∗
2
∗
3
EXTAL pin
∗
4
, TEX pin
∗
5
V
DD
∗
1
This device does not enter the stop mode.
∗
2
PA0 to PA5, PB0 to PB7, PD2, PE0, PE1, PE3, SCL0, SCL1, SDA0, SDA1 pins
∗
3
PA6, PA7, INT2, SCK, SI, PD4, PD5, RMC, EC, INT0, INT1, RST pins
∗
4
Specifies only during external clock input.
∗
5
Specifies only during external event count input.
Recommended Operating Conditions
(Vss = 0V reference)
Supply voltage
Input voltage
Output voltage
Medium drive output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
– 11 –
CXP86609/86613/86617
V
DD
= 4.5V, I
OH
= –0.5mA
V
DD
= 4.5V, I
OH
= –1.2mA
V
DD
= 4.5V, I
OL
= 1.8mA
V
DD
= 4.5V, I
OL
= 3.6mA
V
DD
= 4.5V, I
OL
= 3.0mA
V
DD
= 4.5V, I
OL
= 4.0mA
V
DD
= 5.5V, V
IH
= 5.5V
V
DD
= 5.5V, V
IL
= 0.4V
V
DD
= 5.5V, V
IH
= 5.5V
V
DD
= 4.5V, I
OL
= 12.0mA
High level output
voltage
Low level output
voltage
Input current
I/O leakage current