1
File Number
4804
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. 1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999.
HUF75623P3
22A, 100V, 0.064 Ohm, N-Channel,
UltraFET Power MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.064
Ω,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE
®
and SABER
©
Electrical Models
- Spice and SABER
©
Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JEDEC TO-220AB
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
HUF75623P3
D
G
S
PART NUMBER
PACKAGE
BRAND
HUF75623P3
TO-220AB
75623P
NOTE: When ordering, use the entire part number i.e., HUF75623P3
HUF75623P3
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
100
V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20
V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
22
15
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
0.57
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet
November 1999
2
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 11)
100
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 95V, V
GS
= 0V
-
-
1
µ
A
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
µ
A
Gate to Source Leakage Current
I
GSS
V
GS
=
±
20V
-
-
±
100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 10)
2
-
4
V
Drain to Source On Resistance
r
DS(ON)
I
D
= 22A, V
GS
= 10V (Figure 9)
-
0.054
0.064
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R
θ
JC
TO-220
-
-
1.76
o
C/W
Thermal Resistance Junction to
Ambient
R
θ
JA
-
-
62
o
C/W
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time
t
ON
V
DD
= 50V, I
D
= 22A
V
GS
=
10V,
R
GS
= 13
Ω
(Figures 18, 19)
-
-
75
ns
Turn-On Delay Time
t
d(ON)
-
7.9
-
ns
Rise Time
t
r
-
42
-
ns
Turn-Off Delay Time
t
d(OFF)
-
47
-
ns
Fall Time
t
f
-
39
-
ns
Turn-Off Time
t
OFF
-
-
130
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 20V
V
DD
= 50V,
I
D
= 22A,
I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
-
43
52
nC
Gate Charge at 10V
Q
g(10)
V
GS
= 0V to 10V
-
23
28
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 2V
-
1.7
2
nC
Gate to Source Gate Charge
Q
gs
-
3.5
-
nC
Gate to Drain "Miller" Charge
Q
gd
-
8.7
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
790
-
pF
Output Capacitance
C
OSS
-
215
-
pF
Reverse Transfer Capacitance
C
RSS
-
70
-
pF
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 22A
-
-
1.25
V
I
SD
= 11A
-
-
1.00
V
Reverse Recovery Time
t
rr
I
SD
= 22A, dI
SD
/dt = 100A/
µ
s
-
-
100
ns
Reverse Recovered Charge
Q
RR
I
SD
= 22A, dI
SD
/dt = 100A/
µ
s
-
-
313
nC
HUF75623P3
3
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
T
C
, CASE TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
15
20
25
50
75
100
125
150
0
25
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
175
5
10
0.1
1
2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
10
-5
t, RECTANGULAR PULSE DURATION (s)
Z
θ
JC
, NORMALIZED
THERMAL IMPED
ANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
x R
θ
JC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
300
10
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
I
DM
, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
HUF75623P3
4
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves
(Continued)
10
100
10
300
300
1
1
100
µ
s
10ms
1ms
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
100
100
0.001
0.01
0.1
1
I
AS
, A
V
ALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
10
0
20
30
40
2
3
4
6
I
D,
DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
5
10
0
20
30
40
0
1
2
3
4
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
=5V
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 7V
V
GS
= 6V
V
GS
= 20V
V
GS
= 10V
10
0
1.0
1.5
2.0
3.0
-80
-40
0
40
80
120
200
NORMALIZED DRAIN T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESIST
ANCE
V
GS
= 10V, I
D
= 22A
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
160
2.5
0.5
0.6
0.8
1.0
1.2
-80
-40
0
40
80
120
200
NORMALIZED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
µ
A
THRESHOLD V
O
L
T
A
G
E
160
HUF75623P3
5
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
(Continued)
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
I
D
= 250
µ
A
160
160
20
100
1000
2000
0.1
1.0
10
100
C, CAP
A
CIT
ANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
RSS
=
C
GD
C
OSS
≅
C
DS
+ C
GD
0
2
4
6
8
10
0
5
15
20
25
V
GS
, GA
TE T
O
SOURCE V
O
L
T
A
GE (V)
V
DD
= 50V
Q
g
, GATE CHARGE (nC)
I
D
= 22A
I
D
= 11A
WAVEFORMS IN
DESCENDING ORDER:
10
t
P
V
GS
0.01
Ω
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
HUF75623P3
6
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
V
GS
= 10V
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUF75623P3
7
PSPICE Electrical Model
.SUBCKT HUF75623 2 1 3 ;
rev 26 October 1999
CA 12 8 1.27e-9
CB 15 14 1.27e-9
CIN 6 8 7.20e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 117.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.53e-9
LSOURCE 3 7 4.35e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.70e-2
RGATE 9 20 2.50
RLDRAIN 2 5 10
RLGATE 1 9 55.3
RLSOURCE 3 7 43.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.77e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*43.5),3.5))}
.MODEL DBODYMOD D (IS = 6.0e-13 RS = 6.2e-3 XTI = 5.5 TRS1 = 2.1e-3 TRS2 = 2.0e-6 CJO = 8.50e-10 TT = 6.30e-8 M = 0.54)
.MODEL DBREAKMOD D (RS = 5.6e-1 TRS1 = 8e-4 TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 9.29e-10 IS = 1e-30 M = 0.79)
.MODEL MMEDMOD NMOS (VTO = 3.21 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.50)
.MODEL MSTROMOD NMOS (VTO = 3.60 KP = 37 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.77 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25.0 )
.MODEL RBREAKMOD RES (TC1 =1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 3.00e-5)
.MODEL RSLCMOD RES (TC1 = 3.20e-3 TC2 = 3.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.20e-3 TC2 = -9.00e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.40e-3 TC2 =1.80e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -3.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
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