fn4449

December 1999

HSP50214A

Programmable Downconverter

Features

• Up to 65 MSPS Front-End Processing Rates (CLKIN) and

55 MSPS (41 MSPS Using the Discriminator) Back-End

Processing Rates (PROCCLK)

Clocks May Be Asynchronous

• Processing Capable of >100dB SFDR

• Up to 255-Tap Programmable FIR

• Overall Decimation Factor Ranging from 4 to 16384

• Output Samples Rates to

≅

12.94 MSPS with Output Band-

widths to

≅

982kHz Lowpass

• 32-Bit Programmable NCO for Channel Selection and Car-

rier Tracking

• Digital Resampling Filter for Symbol Tracking Loops and

Incommensurate Sample-to-Output Clock Ratios

• Digital AGC with Programmable Limits and Slew Rate to

Optimize Output Signal Resolution; Fixed or Auto Gain

Adjust

• Serial, Parallel, and FIFO 16-Bit Output Modes

• Cartesian to Polar Converter and Frequency Discriminator

for AFC Loops and Demodulation of AM, FM, FSK, and

DPSK

• Input Level Detector for External I.F. AGC Support

Applications

• Single Channel Digital Software Radio Receivers

• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA

• Compatible with HSP50210 Digital Costas Loop for PSK

Reception

• Evaluation Platform Available

Description

The HSP50214A Programmable Downconverter converts dig-

itized IF data into filtered baseband data which can be pro-

cessed

standard

DSP

microprocessor.

The

Programmable Downconverter (PDC) performs down conver-

sion, decimation, narrowband low pass filtering, gain scaling,

resampling, and Cartesian to Polar coordinate conversion.

The 14-bit sampled IF input is down converted to baseband

by digital mixers and a quadrature NCO, as shown in the

Block Diagram. A decimating (4 to 32) fifth order Cascaded

Integrator-Comb (CIC) filter can be applied to the data

before it is processed by up to 5 decimate-by-2 halfband fil-

ters. The halfband filters are followed by a 255-tap pro-

grammable

FIR

filter.

The

output

data

from

the

programmable FIR filter is scaled by a digital AGC before

being re-sampled in a polyphase FIR filter. The output sec-

tion can provide seven types of data: Cartesian (I, Q), polar

(R, q), filtered frequency (dq/dt), Timing Error (TE), and

AGC level in either parallel or serial format.

Block Diagram

Ordering Information

PART

NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HSP50214AVC

0 to 70

120 Ld MQFP

Q120.28x28

HSP50214AVI

-40 to 85

120 Ld MQFP

Q120.28x28

HALFBAND

POLYPHASE

FIR AND

FILTERS

INPUT

SECTION

LEVEL DETECT

CARRIER

CARTESIAN

OUTPUT FORMA

TTER

DISCRIMINATOR

AGC LOOP FILTER

MAG.

PHASE

RESAMPLING

I OUT

Q OUT

FREQ

AGC

∆

TIMING ERROR

IN(13:0)

REFCLK

SEROUTA

SEROUTB

AOUT(15:0)

BOUT(15:0)

CONTROL

C(7:0)

MICROPROCESSOR

READ/WRITE

GAIN

(2:0)

HALFB

AND

FIL

TERS

FILTER

CIC

ORDER

HALFB

AND

FIL

TERS

POLAR

COORDINATE

CONVERTER

HALFBAND

POLYPHASE

FIR AND

FILTERS

NCO

COF

SOF

ADJ

CLKIN

PROCCLK

255-T

FIR FIL

TER

255-T

FIR FIL

TER

FILTER

CIC

ORDER

File Number

4449.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil Corporation 1999

[ /Title

(HSP5

0214A

)

/Sub-

ject (

Pro-

gram-

mable

Down-

con-

verter)

/Autho

r ()

/Key-

words

(Inter-

sil

Semi-

con-

ductor,

Down-

con-

verter,

Down

Con-

verter,

Pro-

gram-

mable

Down-

con-

verter,

DSP,

AMPS,

TDMA

, North

Ameri-

can

OBSOLETE PR

ODUCT

POSSIBLE SUBSTITUTE PR

ODUCT

HSP50214B

Pinout

120 LEAD MQFP

TOP VIEW

100

106

107

108

109

110

111

101

102

103

104

105

117

118

119

120

112

113

114

115

116

BOUT3

BOUT2

BOUT1

OEBL

BOUT0

BOUT4

GND

PROCCLK

MSYNCI

GND

BOUT7

BOUT6

BOUT5

GND

MSYNCO

GND

BOUT15

BOUT14

BOUT12

BOUT11

BOUT10

BOUT9

BOUT8

BOUT13

OEBH

DATARDY

SYNCOUT

INTRRP

GND

SEL2

SEL1

SEL0

GND

SER

OUT

SER

OUTB

SERSYNC

SER

SERCLK

SYNCIN2

SYNCIN1

COF

GAINADJ0

COFSYNC

GND

SOF

SOFSYNC

IN0

IN1

GND

IN3

CLKIN

GND

ENI

GAINADJ2

IN4

IN8

IN9

IN10

GND

IN7

IN6

IN5

IN2

OEAL

GND

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

GND

OUT10

OUT11

OUT12

IN11

OUT13

OUT14

OUT15

OEAH

GND

REFCLK

GCGNSEL

IN13

IN12

GAINADJ1

HSP50214A

Pin Descriptions

NAME

TYPE

DESCRIPTION

Positive Power Supply Voltage.

GND

Ground.

CLKIN

Input Clock. This clock should be a multiple of the input sample rate. All input section processing oc-

curs on the rising edge of CLKIN. The frequency of CLKIN is designated f

CLKIN

IN(13:0)

Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the

MSB (see Control Word 0).

ENI

Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or inter-

polated (see Control Word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted.

The input sample rate is designated f

, which can be different from f

CLKIN

When ENI is used.

GAINADJ(2:0)

GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added

to the shift code from the microprocessor (

P) interface. The shift code is saturated to a maximum

code of F. The gain is offset by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust)

GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section.

PROCCLK

Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Pro-

cessing is performed on PROCCLK’s rising edge. All output timing is derived from this clock.

NOTE: This clock may be asynchronous to CLKIN.

AGCGNSEL

AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative

to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1.

COF

Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the

Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold

times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

COFSYNC

Carrier Offset Frequency Sync. This signal is asserted one CLK before the most signiﬁcant bit (MSB)

of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to

CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

SOF

Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the

Re-Sampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup

and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210

Costas loop [1].

SOFSYNC

Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset

frequency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK.

This input is compatible with the output of the HSP50210 Costas loop [1].

AOUT(15:0)

Parallel Output Bus A. Two parallel output modes are available on the HSP50214A. The ﬁrst is called

the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-

sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).

The most signiﬁcant byte of AOUT always outputs the most signiﬁcant byte of the Parallel Direct Out-

put Port whose data type is selected via

P interface. AOUT15 is the MSB. In this mode, the

AOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.

The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port

acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,

and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the

Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered

output mode and can be used for buffered mode while the MSBytes are outputting data in the direct

output mode.

BOUT(15:0)

Parallel Output Bus B. Two parallel output modes are available on the HSP50214A. The ﬁrst is called

the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces-

sor Write Section) and comes directly from the Output MUX Section (see Output Control Section).

The most signiﬁcant byte of BOUT always outputs the most signiﬁcant byte of the Parallel Direct Out-

put Port whose data type is selected via

P interface. BOUT15 is the MSB. In this mode, the

BOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted to indicate new data.

The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port

acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase,

and frequency information; a particular information is selected using SEL(2:0). Up to 7 data sets is

stored in the Buffer RAM Output Port. The least signiﬁcant byte of BOUT can be used to either output

the least signiﬁcant byte of the B Parallel Direct Output Port or the least signiﬁcant byte of the Buffer

RAM Output Port. See Output Section.

HSP50214A

DATARDY

Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is

available. DATARDY is asserted for one PROCCLK cycle during the ﬁrst clock cycle that data is avail-

able on the parallel out busses. See Output Section.

OEAH

Output enable for the MSByte of the AOUT bus. Active Low.

OEAL

Output enable for the LSByte of the AOUT bus. Active Low.

OEBH

Output enable for the MSByte of the BOUT bus. Active Low.

OEBL

Output enable for the LSByte of the BOUT bus. Active Low.

SEL(2:0)

Select Address is used to choose which information in a data set from the Buffer RAM Output Port is

sent to the least signiﬁcant bytes of AOUT and BOUT. SEL2 is the MSB.

INTRRP

Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM

Output Port is ready for reading.

SEROUTA

Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can

be sequenced in programmable order. See Output Section and Microprocessor Write Section.

SEROUTB

Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency,

timing error and AGC information can be sequenced in programmable order. See Output Section and

Microprocessor Write Section.

SERCLK

Output Clock for Serial Data Out. Derived from PROCCLK as given by Control Word 20 in the Micro-

processor Write Section.

SERSYNC

Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor

Write Section.

SEROE

Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are

set to a high impedance.

C(7:0)

I/O

Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB.

A(2:0)

Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.

Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in the Pro-

grammable Down Converter on the rising edge of this signal. See Microprocessor Write Section.

Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0)

in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read

Section.

REFCLK

Reference Clock. Used as an input clock for the timing error detector. The timing error is computed

relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2.

MSYNCO

Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are

asynchronous. MSYNCO is the synchronization signal between the input section operating under

CLKIN and the back end processing operating under PROCCLK. This output sync signal from one

part is connected to the MSYNCI signal of all the HSP50214As.

MSYNCI

Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.

NOTE: MSYNCI must be connected to an MSYNCO signal for operation.

SYNCIN1

CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO

update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro-

cessor Write Section. Active High.

SYNCIN2

FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO

update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization

Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High.

SYNCOUT

Strobe Output. This synchronization signal is generated by the

P interface for synchronizing multiple

parts. Can be generated by PROCLK or CLKIN (see Control Word 0 and Control Word 24 in the Mi-

croprocessor Write Section). Active High.

Pin Descriptions

(Continued)

NAME

TYPE

DESCRIPTION

HSP50214A

----

 

 

atan

AOUT(15:0)

BOUT(15:0)

LEVEL

LIMIT

LOOP

FILTER

ERROR

DETECT

NCO

(SYMBOL TRACKING)

MIXER

DECIMATE

FROM 4-32

5TH ORDER

CIC

0 TO 5 HALFBAND FILTER;

DECIMATION UP TO 32

255-TAP

PROGRAMMABLE

FIR FILTER

AGC

RE-SAMPLER

CARTESIAN

POLAR

DISCRIMINATOR

INTERPOLATE

BY 2/4

HALFBAND

(DECIMATE UP TO 16)

IN(13:0)

SEROUTA

SEROUTB

C(7:0)

CONTROL

SECTION

OUTPUT SECTION

CIC, HALFBAND FILTER, AND FIR SECTIONS

INPUT SECTION

SYNCHRONIZATION SECTION

LEVEL DETECT SECTION

DIGITAL AGC SECTION

DISCRIMINATOR SECTION

RE-SAMPLER/INTERPOLATION HALFBAND SECTION

COF

SOF

POL

YPHASE

FIL

TER

CLKIN

PROCCLK

COFSYNC

SOFSYNC

A(2:0)

REFCLK

INPUT

SECTION

GAINADJ(2:0)

AGCGNSEL

ENI

(CARRIER TRACKING)

MSYNCI

MSYNCO

SYNCOUT

SYNCIN1

SYNCIN2

MICROPROCESSOR

READ/WRITE

SEL(2:0)

SERCLK

SERSYNC

SEROE

OEAH

OEAL

OEBH

OEBL

CARRIER NCO SECTIONS

INTRRP

COS

SIN

DIFFERENCE

TIMING ERROR

AGCOUT

TO OUTPUT FORMATTER

AGCOUT

AND MICROPROCESSOR

INTERFACE

DETECT

NCO

CLKIN

PROCCLK

PROCESSOR

INTERFACE

SHIFT

63-TAP

PROGRAMMABLE

FIR FILTER

INTRRP

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214A PROGRAMMABLE DOWNCONVERTER

OUTPUT FORMA

TTER

CHIP

CIRCUITRY

SYNCHRONIZATION

FRONT END

CIRCUITRY

SYNCHRONIZATION

BACK END

CIRCUITRY

SYNCHRONIZATION

POL

YPHASE

FIL

TER

TIMING NCO

DATARDY

= 1;

= 0)

= 1;

= 0)

FILTERS

Functional Description

The HSP50214A Programmable Downconverter (PDC) is an

agile digital tuner designed to meet the requirements of a

wide variety of communications industry standards. The

PDC contains the processing functions needed to convert

sampled IF signals to baseband digital samples. These func-

tions include LO generation/mixing, decimation ﬁltering, pro-

grammable FIR shaping/bandlimiting ﬁltering, resampling,

Automatic Gain Control (AGC), frequency discrimination and

detection

well

multi-chip

synchronization.

The

HSP50214A interfaces directly with a DSP microprocessor

to pass baseband and status data.

A top level functional block diagram of the HSP50214A is

shown in Figure 1. The diagram shows the major blocks and

multiplexers used to reconﬁgure the data path for various

architectures. The HSP50214A can be broken into 13 sec-

tions: Synchronization, Input, Input Level Detector, Carrier

Mixer/Numerically Control Oscillator (NCO), CIC Decimating

Filter, Halfband Decimating Filter, 255-Tap Programmable

FIR Filter, Automatic Gain Control (AGC), Re-sampler/Half-

band Filter, Timing NCO, Cartesian to Polar Converter, Dis-

criminator, and Output Sections. All of these sections are

conﬁgured through a microprocessor interface.

The HSP50214A has three clock inputs; two are required and

one is optional. The input level detector, carrier NCO, and CIC

decimating filter sections operate on the rising edge of the

input clock, CLKIN. The halfband filter, programmable FIR fil-

ter, AGC, Re-Sampler/Halfband filters, timing NCO, discrimi-

nator, and output sections operate on the rising edge of

PROCCLK. The third clock, REFCLK, is used to generate tim-

ing error information.

NOTE: All of the clocks may be asynchronous.

PDC Applications Overview

This section highlights the motivation behind the key program-

mable features from a communications system level perspec-

tive. These motivations will be defined in terms of ability to

provide DSP processing capability for specific modulation for-

mats and communication applications. The versatility of the

Programmable Downconverter can be intimidating because of

the many Control Words required for chip configuration. This

section provides system level insight to help allay reservations

about this versatile DSP product. It should help the designer

capitalize on the greatest feature of the PDC - VERSATILITY

THROUGH PROGRAMMABILITY. It is this feature, when fully

understood, that brings the greatest return on design invest-

ment by offering a single receiver design that can process the

many waveforms required in the communications marketplace.

FDM Based Standards and Applications

Table 1 provides an overview of some common frequency

division multiplex (FDM) base station applications to which the

PDC can be applied. The PDC provides excellent selectivity

for frequency division multiple access (FDMA) signals. This

high selectivity is achieved with 0.012Hz resolution frequency

control of the NCO and the sharp filter responses capable

with a 255-tap, 22-bit coefficient FIR filter. The 16-bit resolu-

tion out of the Cartesian to Polar Coordinate Converter are

routed to the frequency detector, which is followed by a 63-

tap, 22-bit coefficient FIR filter structure for facilitating FM and

FSK detection. The 14-bit input resolution is the smallest bit

resolution found throughout the conversion and filtering sec-

tions, providing excellent dynamic range in the DSP process-

ing. A unique input gain scaler adds an additional 42dB of

range to the input level variation, to compensate for changes

in the analog RF front end receive equipment. Synchroniza-

tion circuitry allows precise timing control of the base station

reconfiguration for all receive channels simultaneously. Por-

tions of this table were corroborated with reference [2].

TDM Based Standards and Applications

Table 2 provides an overview of some common Time Divi-

sion Multiplexed (TDM) base station applications to which

the PDC can be applied. For time division multiple access

(TDMA) applications, such as North American TDMA

(IS136), where 30kHz is the received band of interest for the

PCS basestation, the PDC offers 0.012Hz frequency resolu-

tion in downconversion in addition to

= 0.35 matched (pro-

grammable) ﬁltering capability. The

/4 DPSK modulation

can be processed using the PDC Cartesian to Polar coordi-

nate converter and d

/dt detector circuitry or by processing

the I/Q samples in the DSP

P. The PDC provides the ability

to change the received signal gain and frequency, synchro-

nous with burst timing. The synchronous gain adjustment

allows the user to measure the power of the signal at the A/D

at the end of a burst, and synchronously reload that same

gain value at the arrival of the next user burst.

For applications other than cellular phones (where the pre-

ambles are not changed), the PDC frequency discriminator

output can be used to obtain correlation on the preamble

pattern to aid in burst acquisition.

TABLE 1. CELLULAR PHONE BASE STATION APPLICATIONS

USING FDMA

STANDARD

AMPS

(IS-91)

MCS-L1

MCS-L2

NMT-400

NMT-900

C450

ETACS

NTACS

RX BAND

(MHz)

824-849

925-940

453-458

890-915

451-456

871-904

915-925

CHANNEL

BW (kHz)

25.0

12.5

20.0

10.0

25.0

12.5

# TRAFFIC

CHANNELS

832

600

1200

200

1999

222

444

1240

800

VOICE

MODULA-

TION

PEAK

DEVIATION

(kHz)

9.5

CONTROL

MODULA-

TION

FSK

PEAK

DEVIATION

(kHz)

4.5

3.5

2.5

6.4

CONTROL

CHANNEL

RATE

(Kbps)

0.3

1.2

5.3

HSP50214A

Several applications are combinations of frequency and time

domain multiple access schemes. For example, GSM is a

TDMA signal that is frequency hopped. The individual chan-

nels contain Gaussian MSK modulated signals. The PDC

again offers the 0.012Hz tuning resolution for de-hopping the

received signal. The combination of halfband and 256-tap

programmable, 22-bit coefﬁcient FIR ﬁlters readily performs

the necessary matched ﬁltering for demodulation and opti-

mum detection of the GMSK signals.

CDMA Based Standards and Applications

For Code Division Multiple Access (CDMA) type signals, the

PDC offers the ability to have a single wideband RF front

end, from which it can select a single spread channel of

interest. The synchronization circuitry provides for easy con-

trol of multiple PDC for applications where multiple received

signals are required, such as base-stations.

In IS-95 CDMA, the receive signal bandwidth is approxi-

mately 1.2288MHz wide with many spread spectrum chan-

nel in the band. The PDC supplies the downconversion and

ﬁltering required to receive a single RF channel in the pres-

ence of strong adjacent interference. Multiple PDC’s would

be sourced from a single receive RF chain, each processing

a different receive frequency channel. The despreader would

usually follow the PDC. In some very speciﬁc applications,

with short, ﬁxed codes, the ﬁltering and despreading may be

possible with innovative use of the programmable, 22-bit

coefﬁcient FIR ﬁlter. The PDC offers 0.012Hz resolution on

tuning to the desired receive channel and excellent rejection

of the portions of the band not being processed, via the half-

band and 255-tap programmable, 22-bit coefﬁcient FIR ﬁlter.

Traditional Modulation Formats

AM, ASK, FM and FSK

The PDC has the capability to fully demodulate AM and FM

modulated waveforms. The PDC outputs 15 bits of amplitude or

16 bits of frequency for these modulation formats. The FM dis-

criminator has a 63-tap programmable, 22-bit coefficient FIR fil-

ter for additional signal conditioning of the FM signal. Digital

versions of these formats, ASK and FSK are also readily pro-

cessed using the PDC. Just as in the AM modulated case, ASK

signals will use 15-bit magnitude output of the Cartesian to

Polar Coordinate converter. Multi-tone FSK can be processed

several ways. The frequency information out of the discrimina-

tor can be used to identify the received tone, or the filter can be

used to identify and power detect a specific tone of the received

signal. AMPS is an example of an FM application.

PM and PSK

The PDC provides the downconversion, demodulation,

matched ﬁltering and coordinate conversion required for

demodulation of PM and PSK modulated waveforms. These

modulation formats will require external carrier and symbol

timing recovery loop ﬁlters to complete the receiver design.

The PDC was designed to interface with the HSP50210 Dig-

ital Costas Loop to implement the carrier phase and symbol

timing recovery loop ﬁlters (for continuous PSK signals - not

burst).

Digital modulation formats that combine amplitude and

phase for symbol mappin