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3-34
File Number
3949.7
HI5721
10-Bit, 125 MSPS, High Speed D/A
Converter
The HI5721 is a 10-bit, 125 MSPS, high speed D/A
converter. The converter incorporates a 10-bit, input data
register with quadrature data logic capability and current
outputs. The HI5721 features low glitch energy and excellent
frequency domain specifications.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125 MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.5 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . 0.5ns
• Excellent Spurious Free Dynamic Range
• Improved Second Source for the AD9721
Applications
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• HDTV
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
HI5721
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HI5721BIP
-40 to 85
28 Ld PDIP
E28.6
HI5721BIB
-40 to 85
28 Ld SOIC (W)
M28.3
HI5721-EVP
25
Evaluation Board (PDIP)
HI5721-EVS
25
Evaluation Board (SOIC)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
CLOCK
NC
INVERT
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
CTRL AMP IN
REF OUT
CTRL AMP OUT
REF IN
I
OUT
ARTN
AGND
R
SET
DV
EE
DGND
DV
EE
AV
EE
I
OUT
Data Sheet
June 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999
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3-35
Typical Applications Circuit
Functional Block Diagram
D7 (3)
D6 (4)
D5 (5)
D4 (6)
D3 (7)
D2 (8)
D1 (9)
D0 (LSB) (10)
D7
D6
D5
D4
D3
D2
D1
D0
+5V
V
CC
(14)
0.01
µ
F
DGND (15, 28)
CLK (11)
INVERT (13)
-5.2V (AV
EE
)
0.1
µ
F
(19) ARTN
(22) AV
EE
D/A OUT
(20) I
OUT
(21) I
OUT
(17) R
SET
1960
Ω
64
Ω
(26) CTRL AMP IN
(23) REF IN
HI5721
D8
D9
D9 (MSB) (1)
D8 (2)
DV
EE
(16, 27)
- 5.2V (AV
EE
)
0.01
µ
F
(24) CTRL AMP OUT
(25) REF OUT
64
Ω
0.1
µ
F
- 5.2V (DV
EE
)
0.01
µ
F
0.1
µ
F
(18) AGND
50
Ω
UPPER
VOLTAGE
REFERENCE
REF IN
I
OUT
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D9
INVERT
CLK
D7
D8
4-BIT
DECODER
I
OUT
QUADRATURE
LOGIC
+
-
CTRL AMP
REF OUT
R
SET
CTRL AMP IN
25
Ω
DATA
BUFFER/
LEVEL
SHIFTER
OUT
15
SWITCHED
CURRENT
CELLS
6 LSBs
CURRENT
CELLS
SLAVE
REGISTER
AV
EE
AGND
DV
EE
DGND
V
CC
R2R
NETWORK
227
Ω
227
Ω
15
15
ARTN
HI5721
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3-36
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage V
CC
to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DV
EE
to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AV
EE
to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D9-D0, CLK, INVERT) . . . . . . . V
CC
to -0.5 V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . .500
µ
A
Control Amplifier Input Voltage Range. . . . . . . . . . . . AGND to -4.0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . .
±
2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . -3.7 V to AV
EE
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Power Dissipation
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750mW
Maximum Junction Temperature
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, CTRL AMP IN = REF OUT,
T
A
= 25
o
C for All Typical Values
PARAMETER
TEST CONDITIONS
HI5721BI
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
10
-
-
Bits
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
±
0.5
±
1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
±
0.5
±
1.0
LSB
Offset Error, I
OS
(Note 4)
-
16
75
µ
A
Full Scale Gain Error, FSE
(Notes 2, 4)
-
2
10
%
Offset Drift Coefficient
(Note 3)
-
0.1
-
µ
A/
o
C
Full Scale Output Current, I
FS
-
-20.48
-
mA
Output Voltage Compliance Range
(Note 3)
-1.5
-
+3.0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
125.0
-
-
MSPS
Output Voltage Full Scale Step Settling Time, t
SETT FS
To
±
0.5 LSB Error Band R
L
= 50
Ω
(Note 3)
-
4.5
-
ns
Output Voltage Small Step Settling Time, t
SETT SM
100mV Step to
±
0.5 LSB Error Band, R
L
= 50
Ω
(Note 3)
-
3.5
-
ns
Singlet Glitch Area, GE (Peak Glitch)
R
L
= 50
Ω
(Note 3)
-
3.5
-
pV•s
Doublet Glitch Area, (Net Glitch)
-
1.5
-
pV•s
Output Slew Rate
R
L
= 50
Ω,
DAC Operating in Latched Mode
(Note 3)
-
1,000
-
V/
µ
s
Output Rise Time
R
L
= 50
Ω,
DAC Operating in Latched Mode
(Note 3)
-
675
-
ps
Output Fall Time
R
L
= 50
Ω,
DAC Operating in Latched Mode
(Note 3)
-
470
-
ps
HI5721
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3-37
Spurious Free Dynamic Range, SFDR to Nyquist
f
CLK
= 125 MSPS, f
OUT
= 2.02MHz, 62.5MHz
Span (Notes 3, 5)
-
-59
-
dBc
f
CLK
= 125 MSPS, f
OUT
= 25MHz, 62.5MHz Span
(Notes 3, 5)
-
-53
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz, 50MHz Span
(Notes 3, 5)
-
-59
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 25MHz, 50MHz Span
(Notes 3, 5)
-
-51
-
dBc
Spurious Free Dynamic Range, SFDR Within a
Window
f
CLK
= 125 MSPS, f
OUT
= 2.02MHz, 2MHz Span
(Notes 3, 5)
-
-75
-
dBc
f
CLK
= 125 MSPS, f
OUT
= 25MHz, 2MHz Span
(Notes 3, 5)
-
-70
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz, 2MHz Span
(Notes 3, 5)
-
-75
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 25MHz, 2MHz Span
(Notes 3, 5)
-
-72
-
dBc
Signal to Noise Ratio (SNR) to Nyquist
(Ignoring the First 5 Harmonics)
f
CLK
= 125 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
54
-
dB
f
CLK
= 125 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
51.5
-
dB
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
54.5
-
dB
f
CLK
= 100 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
50.3
-
dB
Signal to Noise Ratio + Distortion (SINAD) to Nyquist
f
CLK
= 125 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
52.4
-
dB
f
CLK
= 125 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
49.2
-
dB
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
52.7
-
dB
f
CLK
= 100 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
47.6
-
dB
Total Harmonic Distortion (THD) to Nyquist
f
CLK
= 125 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
-57.8
-
dBc
f
CLK
= 125 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
-53.3
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz,
(Notes 3, 5)
-
-57.9
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 25MHz
(Notes 3, 5)
-
-51
-
dBc
Intermodulation Distortion (IMD) to Nyquist
f
CLK
= 125 MSPS, f
OUT1
= 800kHz,
f
OUT2
= 900kHz (Notes 3, 5)
-
57.3
-
dB
f
CLK
= 100 MSPS, f
OUT1
= 800kHz,
f
OUT2
= 900kHz (Notes 3, 5)
-
57.2
-
dB
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, CTRL AMP IN = REF OUT,
T
A
= 25
o
C for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
HI5721BI
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HI5721
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3-38
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, REF OUT
(Note 4)
-1.15
-1.25
-1.35
V
Internal Reference Voltage Drift
(Note 3)
-
100
-
µ
V/
o
C
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-50
-
+500
µ
A
Amplifier Input Impedance
(Note 3)
-
10
-
M
Ω
Amplifier Large Signal Bandwidth
4.0V
P-P
Sine Wave Input, to Slew Rate Limited
(Note 3)
-
1
-
MHz
Amplifier Small Signal Bandwidth
1.0V
P-P
Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
4.6
-
k
Ω
Reference Input Multiplying Bandwidth
R
L
= 50
Ω
, 100mV Sine Wave, to -3dB Loss at
I
OUT
(Note 3)
-
75
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
(Note 4)
2.0
-
-
V
Input Logic Low Voltage, V
IL
(Note 4)
-
-
0.8
V
Input Logic Current, I
IH
(Note 4)
-
-
400
µ
A
Input Logic Current, I
IL
(Note 4)
-
-
700
µ
A
Digital Input Capacitance, C
IN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, t
SU
See Figure 3 (Note 3)
2.0
-
-
ns
Data Hold Time, t
HLD
See Figure 3 (Note 3)
0.5
-
-
ns
Propagation Delay Time, t
PD
See Figure 3 (Note 3)
-
4.5
-
ns
CLK Pulse Width, t
PW1
, t
PW2
See Figure 3 (Note 3)
1.0
0.85
-
ns
POWER SUPPLY CHARACTERISITICS
IDV
EE
(Note 4)
-
100
110
mA
IAV
EE
(Note 4)
-
-
15
mA
V
CC
(Note 4)
-
14
25
mA
Power Dissipation
(Note 4)
-
700
775
mW
Power Supply Rejection Ratio
V
CC
±
5%, V
EE
±
5%
-
50
-
µ
A/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 640
µ
A). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25
o
C. 100% productions tested at temperature extremes for military temperature devices, sample tested for in-
dustrial temperature devices.
5. Spectral measurements made without external filtering.
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, CTRL AMP IN = REF OUT,
T
A
= 25
o
C for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
HI5721BI
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HI5721
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3-39
Timing Diagrams
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D9-D0
I
OUT
50%
t
SETT
1
/
2
LSB ERROR BAND
t
PD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA =
1
/
2
(H x W)
CLK
D9-D0
I
OUT
50%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
PD
t
PD
t
HLD
t
HLD
t
SETT
t
SETT
t
SETT
HI5721
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3-40
Typical Performance Curves
FIGURE 4. INTEGRAL NON-LINERARITY “BEST FIT”
STRAIGHT LINE
FIGURE 5. DIFFERENTIAL NON-LINEARITY
FIGURE 6. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST
25MHz FUNDAMENTAL
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST
2MHz FUNDAMENTAL
FIGURE 8. INTERMODULATION DISTORTION
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE (TO NYQUIST)
vs OUTPUT FREQUENCY
1023
DATA CODE
1.0
0.5
0
-0.5
-1.0
LSB
0
200
600
800
400
1023
DATA CODE
+0.5
0.2
0
-0.2
-0.5
LSB
0
200
600
800
400
0.4
-0.4
dB
START 0Hz
STOP 62.50MHz
†
RBW 3.0kHz
†
VBW 1kHz
SWP 53.0s
†
ATTEN 20dB
RL -10.0dBm
10dB/
∆
MKR -54.16dB
25.2MHz
HI-5721
f
CLK
= 125 MSPS
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
OUT
= 25 MHZ
START 0Hz
STOP 62.50MHz
†
RBW 3.0kHz
†
VBW 1.0kHz
SWP 53.0s
†
ATTEN 20dB
RL -10.0dBm
10dB/
SFDR = -55.8dBc
HI-5721
f
CLK
= 125 MSPS
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
dB
-110
f
OUT
= 2 MHz
FREQUENCY (MHz)
0.0
-20
-40
-60
-110
dB
0
2
6
4
-80
-100
800kHz
900kHz
f
1
= 800kHz
f
2
= 900kHz
f
OUT
(MHz)
60
59
58
57
56
55
54
53
52
51
50
49
48
f
CLK
= 125 MSPS
f
CLK
= 100 MSPS
dBc
2
24
10
12
4
6
14
16
20
8
26
18
22
HI5721
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3-41
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE
(
±
1MHz WINDOW) vs FREQUENCY