DP8390D/NS32490D NIC Network Interface Controller

TL F 8582

DP8390DNS32490D

NIC

Network

Interface

Controller

July 1995

DP8390D NS32490D NIC Network Interface Controller

General Description

The DP8390D NS32490D Network Interface Controller

(NIC) is a microCMOS VLSI device designed to ease inter-

facing with CSMA CD type local area networks including

Ethernet Thin Ethernet (Cheapernet) and StarLAN The

NIC implements all Media Access Control (MAC) layer func-

tions for transmission and reception of packets in accord-

ance with the IEEE 802 3 Standard Unique dual DMA chan-

nels and an internal FIFO provide a simple yet efficient

packet management design To minimize system parts

count and cost all bus arbitration and memory support logic

are integrated into the NIC

The NIC is the heart of a three chip set that implements the

complete IEEE 802 3 protocol and node electronics as

shown below The others include the DP8391 Serial Net-

work Interface (SNI) and the DP8392 Coaxial Transceiver

Interface (CTI)

Features

Compatible with IEEE 802 3 Ethernet II Thin Ethernet

StarLAN

Interfaces with 8- 16- and 32-bit microprocessor

systems

Implements simple versatile buffer management

Requires single 5V supply

Utilizes low power microCMOS process

Includes

Two 16-bit DMA channels

16-byte internal FIFO with programmable threshold

Network statistics storage

Supports physical multicast and broadcast address

filtering

Provides 3 levels of loopback

Utilizes independent system and network clocks

Table of Contents

1 0 SYSTEM DIAGRAM

2 0 BLOCK DIAGRAM

3 0 FUNCTIONAL DESCRIPTION

4 0 TRANSMIT RECEIVE PACKET ENCAPSULATION

DECAPSULATION

5 0 PIN DESCRIPTIONS

6 0 DIRECT MEMORY ACCESS CONTROL (DMA)

7 0 PACKET RECEPTION

8 0 PACKET TRANSMISSION

9 0 REMOTE DMA

10 0 INTERNAL REGISTERS

11 0 INITIALIZATION PROCEDURES

12 0 LOOPBACK DIAGNOSTICS

13 0 BUS ARBITRATION AND TIMING

14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS

15 0 SWITCHING CHARACTERISTICS

16 0 PHYSICAL DIMENSIONS

1 0 System Diagram

IEEE 802 3 Compatible Ethernet Thin Ethernet Local Area Network Chip Set

TL F 8582 – 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

2 0 Block Diagram

TL F 8582 – 2

FIGURE 1

3 0 Functional Description

(Refer to

Figure 1 )

RECEIVE DESERIALIZER

The Receive Deserializer is activated when the input signal

Carrier Sense is asserted to allow incoming bits to be shift-

ed into the shift register by the receive clock The serial

receive data is also routed to the CRC generator checker

The Receive Deserializer includes a synch detector which

detects the SFD (Start of Frame Delimiter) to establish

where byte boundaries within the serial bit stream are locat-

ed After every eight receive clocks the byte wide data is

transferred to the 16-byte FIFO and the Receive Byte Count

is incremented

The first six bytes after the SFD are

checked for valid comparison by the Address Recognition

Logic If the Address Recognition Logic does not recognize

the packet the FIFO is cleared

CRC GENERATOR CHECKER

During transmission the CRC logic generates a local CRC

field for the transmitted bit sequence The CRC encodes all

fields after the synch byte The CRC is shifted out MSB first

following the last transmit byte During reception the CRC

logic generates a CRC field from the incoming packet This

local CRC is serially compared to the incoming CRC ap-

pended to the end of the packet by the transmitting node If

the local and received CRC match a specific pattern will be

generated and decoded to indicate no data errors Trans-

mission errors result in a different pattern and are detected

resulting in rejection of a packet

TRANSMIT SERIALIZER

The Transmit Serializer reads parallel data from the FIFO

and serializes it for transmission The serializer is clocked by

the transmit clock generated by the Serial Network Interface

(DP8391) The serial data is also shifted into the CRC gen-

erator checker At the beginning of each transmission the

Preamble and Synch Generator append 62 bits of 1 0 pre-

amble and a 1 1 synch pattern After the last data byte of

the packet has been serialized the 32-bit FCS field is shifted

directly out of the CRC generator In the event of a collision

the Preamble and Synch generator is used to generate a

32-bit JAM pattern of all 1’s

ADDRESS RECOGNITION LOGIC

The address recognition logic compares the Destination Ad-

dress Field (first 6 bytes of the received packet) to the Phys-

ical address registers stored in the Address Register Array

If any one of the six bytes does not match the pre-pro-

grammed physical address the Protocol Control Logic re-

jects the packet All multicast destination addresses are fil-

tered using a hashing technique (See register description )

If the multicast address indexes a bit that has been set in

the filter bit array of the Multicast Address Register Array

the packet is accepted otherwise it is rejected by the Proto-

col Control Logic Each destination address is also checked

for all 1’s which is the reserved broadcast address

FIFO AND FIFO CONTROL LOGIC

The NIC features a 16-byte FIFO During transmission the

DMA writes data into the FIFO and the Transmit Serializer

reads data from the FIFO and transmits it During reception

the Receive Deserializer writes data into the FIFO and the

DMA reads data from the FIFO The FIFO control logic is

used to count the number of bytes in the FIFO so that after

a preset level the DMA can begin a bus access and write

read data to from the FIFO before a FIFO underflow

over-

flow occurs

3 0 Functional Description

(Continued)

Because the NIC must buffer the Address field of each in-

coming packet to determine whether the packet matches its

Physical Address Registers or maps to one of its Multicast

Registers the first local DMA transfer does not occur until 8

bytes have accumulated in the FIFO

To assure that there is no overwriting of data in the FIFO

the FIFO logic flags a FIFO overrun as the 13th byte is

written into the FIFO this effectively shortens the FIFO to

13 bytes In addition the FIFO logic operates differently in

Byte Mode than in Word Mode In Byte Mode a threshold is

indicated when the n

1 byte has entered the FIFO thus

with an 8-byte threshold the NIC issues Bus Request

(BREQ) when the 9th byte has entered the FIFO For Word

Mode BREQ is not generated until the n

2 bytes have

entered the FIFO Thus with a 4 word threshold (equivalent

to an 8-byte threshold) BREQ is issued when the 10th byte

has entered the FIFO

PROTOCOL PLA

The protocol PLA is responsible for implementing the IEEE

802 3 protocol including collision recovery with random

backoff The Protocol PLA also formats packets during

transmission and strips preamble and synch during recep-

tion

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two

16-bit DMA channels During reception the Local DMA

stores packets in a receive buffer ring located in buffer

memory During transmission the Local DMA uses pro-

grammed pointer and length registers to transfer a packet

from local buffer memory to the FIFO A second DMA chan-

nel is used as a slave DMA to transfer data between the

local buffer memory and the host system The Local DMA

and Remote DMA are internally arbitrated with the Local

DMA channel having highest priority Both DMA channels

use a common external bus clock to generate all required

bus timing External arbitration is performed with a standard

bus request bus acknowledge handshake protocol

4 0 Transmit Receive Packet

Encapsulation Decapsulation

A standard IEEE 802 3 packet consists of the following

fields preamble Start of Frame Delimiter (SFD) destination

address source address length data and Frame Check

Sequence (FCS) The typical format is shown in

Figure 2

The packets are Manchester encoded and decoded by the

DP8391 SNI and transferred serially to the NIC using NRZ

data with a clock All fields are of fixed length except for the

data field The NIC generates and appends the preamble

SFD and FCS field during transmission The Preamble and

SFD fields are stripped during reception (The CRC is

passed through to buffer memory during reception )

PREAMBLE AND START OF FRAME DELIMITER (SFD)

The Manchester encoded alternating 1 0 preamble field is

used by the SNI (DP8391) to acquire bit synchronization

with an incoming packet When transmitted each packet

contains 62 bits of alternating 1 0 preamble Some of this

preamble will be lost as the packet travels through the net-

work The preamble field is stripped by the NIC Byte align-

ment is performed with the Start of Frame Delimiter (SFD)

pattern which consists of two consecutive 1’s The NIC

does not treat the SFD pattern as a byte it detects only the

two bit pattern This allows any preceding preamble within

the SFD to be used for phase locking

DESTINATION ADDRESS

The destination address indicates the destination of the

packet on the network and is used to filter unwanted pack-

ets from reaching a node There are three types of address

formats supported by the NIC physical multicast and

broadcast The physical address is a unique address that

corresponds only to a single node All physical addresses

have an MSB of ‘‘0’’ These addresses are compared to the

internally stored physical address registers Each bit in the

destination address must match in order for the NIC to ac-

cept the packet Multicast addresses begin with an MSB of

‘‘1’’ The DP8390D filters multicast addresses using a stan-

dard hashing algorithm that maps all multicast addresses

into a 6-bit value This 6-bit value indexes a 64-bit array that

filters the value If the address consists of all 1’s it is a

broadcast address indicating that the packet is intended for

all nodes A promiscuous mode allows reception of all pack-

ets the destination address is not required to match any

filters Physical broadcast multicast and promiscuous ad-

dress modes can be selected

SOURCE ADDRESS

The source address is the physical address of the node that

sent the packet Source addresses cannot be multicast or

broadcast addresses This field is simply passed to buffer

memory

LENGTH FIELD

The 2-byte length field indicates the number of bytes that

are contained in the data field of the packet This field is not

interpreted by the NIC

DATA FIELD

The data field consists of anywhere from 46 to 1500 bytes

Messages longer than 1500 bytes need to be broken into

multiple packets Messages shorter than 46 bytes will re-

quire appending a pad to bring the data field to the minimum

length of 46 bytes If the data field is padded the number of

valid data bytes is indicated in the length field The NIC

does not strip or append pad bytes for short packets

or check for oversize packets

FCS FIELD

The Frame Check Sequence (FCS) is a 32-bit CRC field

calculated and appended to a packet during transmission to

allow detection of errors when a packet is received During

reception error free packets result in a specific pattern in

the CRC generator Packets with improper CRC will be re-

jected The AUTODIN II (X

polynomial is used for the CRC calculations

TL F 8582 – 3

FIGURE 2

5 0 Pin Descriptions

(Continued)

BUS INTERFACE PINS

(Continued)

Symbol

DIP Pin No

Function

Description

CHIP SELECT

Chip Select places controller in slave mode for mP access to

internal registers Must be valid through data portion of bus cycle RA0 – RA3 are

used to select the internal register SWR and SRD select direction of data

transfer

MWR

O Z

MASTER WRITE STROBE

Strobe for DMA transfers active low during write

cycles (t2 t3 tw) to buffer memory Rising edge coincides with the presence of

valid output data TRI-STATE until BACK asserted

MRD

O Z

MASTER READ STROBE

Strobe for DMA transfers active during read cycles

(t2 t3 tw) to buffer memory Input data must be valid on rising edge of MRD

TRI-STATE until BACK asserted

SWR

SLAVE WRITE STROBE

Strobe from CPU to write an internal register selected

by RA0 – RA3

SRD

SLAVE READ STROBE

Strobe from CPU to read an internal register selected

by RA0 – RA3

ACK

ACKNOWLEDGE

Active low when NIC grants access to CPU Used to insert

WAIT states to CPU until NIC is synchronized for a register read or write

operation

RA0 – RA3

45 – 48

These four pins are used to select a register to be read

or written The state of these inputs is ignored when the NIC is not in slave mode

(CS high)

PRD

PORT READ

Enables data from external latch onto local bus during a memory

write cycle to local memory (remote write operation) This allows asynchronous

transfer of data from the system memory to local memory

WACK

WRITE ACKNOWLEDGE

Issued from system to NIC to indicate that data has

been written to the external latch The NIC will begin a write cycle to place the

data in local memory

INT

INTERRUPT

Indicates that the NIC requires CPU attention after reception

transmission or completion of DMA transfers The interrupt is cleared by writing

to the ISR All interrupts are maskable

RESET

Reset is active low and places the NIC in a reset mode immediately no

packets are transmitted or received by the NIC until STA bit is set Affects

Command Register Interrupt Mask Register Data Configuration Register and

Transmit Configuration Register The NIC will execute reset within 10 BUSK

cycles

BREQ

BUS REQUEST

Bus Request is an active high signal used to request the bus for

DMA transfers This signal is automatically generated when the FIFO needs

servicing

BACK

BUS ACKNOWLEDGE

Bus Acknowledge is an active high signal indicating that

the CPU has granted the bus to the NIC If immediate bus access is desired

BREQ should be tied to BACK Tying BACK to V

will result in a deadlock

PRQ ADS1

O Z

PORT REQUEST ADDRESS STROBE 1

32-BIT MODE If LAS is set in the Data Configuration Register this line is

programmed as ADS1 It is used to strobe addresses A16 – A31 into external

latches (A16 – A31 are the fixed addresses stored in RSAR0 RSAR1 ) ADS1

will remain at TRI-STATE until BACK is received

16-BIT MODE If LAS is not set in the Data Configuration Register this line is

programmed as PRQ and is used for Remote DMA Transfers In this mode

PRQ will be a standard logic output

NOTE This line will power up as TRI-STATE until the Data Configuration

READY

This pin is set high to insert wait states during a DMA transfer The NIC

will sample this signal at t3 during DMA transfers

5 0 Pin Descriptions

(Continued)

BUS INTERFACE PINS

(Continued)

Symbol

DIP Pin No

Function

Description

PWR

PORT WRITE

Strobe used to latch data from the NIC into external latch for

transfer to host memory during Remote Read transfers The rising edge of PWR

coincides with the presence of valid data on the local bus

RACK

READ ACKNOWLEDGE

Indicates that the system DMA or host CPU has read

the data placed in the external latch by the NIC The NIC will begin a read cycle

to update the latch

BSCK

This clock is used to establish the period of the DMA memory cycle Four clock

cycles (t1 t2 t3 t4) are used per DMA cycle DMA transfers can be extended by

one BSCK increments using the READY input

NETWORK INTERFACE PINS

COL

COLLISION DETECT

This line becomes active when a collision has been

detected on the coaxial cable During transmission this line is monitored after

preamble and synch have been transmitted At the end of each transmission this

line is monitored for CD heartbeat

RXD

RECEIVE DATA

Serial NRZ data received from the ENDEC clocked into the

NIC on the rising edge of RXC

CRS

CARRIER SENSE

This signal is provided by the ENDEC and indicates that

carrier is present This signal is active high

RXC

RECEIVE CLOCK

Re-synchronized clock from the ENDEC used to clock data

from the ENDEC into the NIC

LBK

LOOPBACK

This output is set high when the NIC is programmed to perform a

loopback through the StarLAN ENDEC

TXD

TRANSMIT DATA

Serial NRZ Data output to the ENDEC The data is valid on

the rising edge of TXC

TXC

TRANSMIT CLOCK

This clock is used to provide timing for internal operation

and to shift bits out of the transmit serializer TXC is nominally a 1 MHz clock

provided by the ENDEC

TXE

TRANSMIT ENABLE

This output becomes active when the first bit of the

packet is valid on TXD and goes low after the last bit of the packet is clocked out

of TXD This signal connects directly to the ENDEC This signal is active high

POWER

5V DC is required It is suggested that a decoupling capacitor be connected

between these pins It is essential to provide a path to ground for the GND pin

GND

with the lowest possible impedance

6 0 Direct Memory Access Control (DMA)

The DMA capabilities of the NIC greatly simplify use of the

DP8390D in typical configurations The local DMA channel

transfers data between the FIFO and memory On transmis-

sion the packet is DMA’d from memory to the FIFO in

bursts Should a collision occur (up to 15 times) the packet

is retransmitted with no processor intervention On recep-

tion packets are DMAed from the FIFO to the receive buffer

ring (as explained below)

A remote DMA channel is also provided on the NIC to ac-

complish transfers between a buffer memory and system

memory The two DMA channels can alternatively be com-

bined to form a single 32-bit address with 8- or 16-bit data

DUAL DMA CONFIGURATION

An example configuration using both the local and remote

DMA channels is shown below Network activity is isolated

on a local bus where the NIC’s local DMA channel per-

forms burst transfers between the buffer memory and the

NIC’s FIFO The Remote DMA transfers data between the

buffer memory and the host memory via a bidirectional I O

port The Remote DMA provides local addressing capability

and is used as a slave DMA by the host Host side address-

ing must be provided by a host DMA or the CPU The NIC

allows Local and Remote DMA operations to be interleaved

SINGLE CHANNEL DMA OPERATION

If desirable the two DMA channels can be combined to

provide a 32-bit DMA address The upper 16 bits of the 32-

bit address are static and are used to point to a 64k byte (or

32k word) page of memory where packets are to be re-

ceived and transmitted

7 0 Packet Reception

(Continued)

for storing packets is controlled by Buffer Management Log-

ic in the NIC The Buffer Management Logic provides three

basic functions linking receive buffers for long packets re-

covery of buffers when a packet is rejected and recircula-

tion of buffer pages that have been read by the host

At initialization a portion of the 64k byte (or 32k word) ad-

dress space is reserved for the receive buffer ring Two

eight bit registers

the Page Start Address Register

(PSTART) and the Page Stop Address Register (PSTOP)

define the physical boundaries of where the buffers reside

The NIC treats the list of buffers as a logical ring whenever

the DMA address reaches the Page Stop Address the DMA

is reset to the Page Start Address

INITIALIZATION OF THE BUFFER RING

Two static registers and two working registers control the

operation of the Buffer Ring These are the Page Start Reg-

ister Page Stop Register (both described previously) the

Current Page Register and the Boundary Pointer Register

The Current Page Register points to the first buffer used to

store a packet and is used to restore the DMA for writing

status to the Buffer Ring or for restoring the DMA address in

the event of a Runt packet a CRC or Frame Alignment

error The Boundary Register points to the first packet in the

Ring not yet read by the host If the local DMA address ever

reaches the Boundary reception is aborted The Boundary

Pointer is also used to initialize the Remote DMA for remov-

ing a packet and is advanced when a packet is removed A

simple analogy to remember the function of these registers

is that the Current Page Register acts as a Write Pointer and

the Boundary Pointer acts as a Read Pointer

Note 1

At initialization the Page Start Register value should be loaded into

both the Current Page Register and the Boundary Pointer Register

Note 2

The Page Start Register must not be initialized to 00H

Receive Buffer Ring At Initialization

TL F 8582 – 30

BEGINNING OF RECEPTION

When the first packet begins arriving the NIC begins storing

the packet at the location pointed to by the Current Page

allow room for storing receive status corresponding to this

packet

Received Packet Enters Buffer Pages

TL F 8582 – 31

LINKING RECEIVE BUFFER PAGES

If the length of the packet exhausts the first 256 byte buffer

the DMA performs a forward link to the next buffer to store

the remainder of the packet For a maximal length packet

the buffer logic will link six buffers to store the entire packet

Buffers cannot be skipped when linking a packet will always

be stored in contiguous buffers Before the next buffer can

be linked the Buffer Management Logic performs two com-

parisons The first comparison tests for equality between

the DMA address of the next buffer and the contents of the

Page Stop Register If the buffer address equals the Page

Stop Register the buffer management logic will restore the

DMA to the first buffer in the Receive Buffer Ring value

programmed in the Page Start Address Register The sec-

ond comparison tests for equality between the DMA ad-

dress of the next buffer address and the contents of the

Boundary Pointer Register If the two values are equal the

reception is aborted The Boundary Pointer Register can be

used to protect against overwriting any area in the receive

buffer ring that has not yet been read When linking buffers

buffer management will never cross this pointer effectively

avoiding any overwrites If the buffer address does not

match either the Boundary Pointer or Page Stop Address

the link to the next buffer is performed

Linking Buffers

Before the DMA can enter the next contiguous 256 byte

buffer the address is checked for equality to PSTOP and to

the Boundary Pointer If neither are reached the DMA is

allowed to use the next buffer

Linking Receive Buffer Pages

1) Check for

to PSTOP

2) Check for

to Boundary

TL F 8582 – 32

7 0 Packet Reception

(Continued)

Received Packet Aborted if It Hits Boundary Pointer

TL F 8582 – 8

Buffer Ring Overflow

If the Buffer Ring has been filled and the DMA reaches the

Boundary Pointer Address reception of the incoming pack-

et will be aborted by the NIC Thus the packets previously

received and still contained in the Ring will not be de-

stroyed

In a heavily loaded network environment the local DMA may

be disabled preventing the NIC from buffering packets from

the network To guarantee this will not happen a software

reset must be issued during all Receive Buffer Ring over-

flows (indicated by the OVW bit in the Interrupt Status Reg-

ister) The following procedure is required to recover

from a Receiver Buffer Ring Overflow

If this routine is not adhered to the NIC may act in an unpre-

dictable manner It should also be noted that it is not per-

missible to service an overflow interrupt by continuing to

empty packets from the receive buffer without implementing

the prescribed overflow routine A flow chart of the NIC’s

overflow routine can be found at the right

Note

It is necessary to define a variable in the driver which will be called

‘‘Resend’’

1 Read and store the value of the TXP bit in the NIC’s

Command Register

2 Issue the STOP command to the NIC This is accom-

plished be setting the STP bit in the NIC’s Command

the NIC

Note

If the STP is set when a transmission is in progress the RST bit may

not be set In this case the NIC is guaranteed to be reset after the

longest packet time (1500 bytes

1 2 ms) For the DP8390D (but not

for the DP8390B) the NIC will be reset within 2 microseconds after

the STP bit is set and Loopback mode 1 is programmed

3 Wait for at least 1 6 ms Since the NIC will complete any

transmission or reception that is in progress it is neces-

sary to time out for the maximum possible duration of an

Ethernet transmission or reception By waiting 1 6 ms this

is achieved with some guard band added Previously it

was recommended that the RST bit of the Interrupt

Status Register be polled to insure that the pending

transmission or reception is completed This bit is not a

reliable indicator and subsequently should be ignored

4 Clear the NIC’s Remote Byte Count registers (RBCR0

and RBCR1)

TL F 8582 – 95

Overflow Routine Flow Chart

5 Read the stored value of the TXP bit from step 1 above

If this value is a 0 set the ‘‘Resend’’ variable to a 0 and

jump to step 6

If this value is a 1 read the NIC’s Interrupt Status Regis-

ter If either the Packet Transmitted bit (PTX) or Trans-

mit Error bit (TXE) is set to a 1 set the ‘‘Resend’’ vari-

able to a 0 and jump to step 6 If neither of these bits is

set place a 1 in the ‘‘Resend’’ variable and jump to step

This step determines if there was a transmission in prog-

ress when the stop command was issued in step 2 If

there was a transmission in progress the NIC’s ISR is

read to determine whether or not the packet was recog-

nized by the NIC If neither the PTX nor TXE bit was set

7 0 Packet Reception

(Continued)

then the packet will essentially be lost and re-transmit-

ted only after a time-out takes place in the upper level

software By determining that the packet was lost at the

driver level a transmit command can be reissued to the

NIC once the overflow routine is completed (as in step

11) Also it is possible for the NIC to defer indefinitely

when it is stopped on a busy network Step 5 also allevi-

ates this problem Step 5 is essential and should not be

omitted from the overflow routine in order for the NIC to

operate correctly

6 Place the NIC in either mode 1 or mode 2 loopback This

can be accomplished by setting bits D2 and D1 of the

Transmit Configuration Register to ‘‘0 1’’ or ‘‘1 0’’ re-

spectively

7 Issue the START command to the NIC This can be ac-

complished by writing 22H to the Command Register

This is necessary to activate the NIC’s Remote DMA

channel

8 Remove one or more packets from the receive buffer

ring

9 Reset the overwrite warning (OVW overflow) bit in the

Interrupt Status Register

10 Take the NIC out of loopback This is done by writing the

Transmit Configuration Register with the value it con-

tains during normal operation (Bits D2 and D1 should

both be programmed to 0 )

11 If the ‘‘Resend’’ variable is set to a 1 reset the ‘‘Re-

send’’ variable and reissue the transmit command This

is done by writing a value of 26H to the Command Reg-

ister If the ‘‘Resend’’ variable is 0 nothing needs to be

done

Note

If Remote DMA is not being used the NIC does not need to be started

before packets can be removed from the receive buffer ring Hence

step 8 could be done before step 7

END OF PACKET OPERATIONS

At the end of the packet the NIC determines whether the

received packet is to be accepted or rejected It either

branches to a routine to store the Buffer Header or to anoth-

er routine that recovers the buffers used to store the packet

SUCCESSFUL RECEPTION

If the packet is successfully received as shown the DMA is

restored to the first buffer used to store the packet (pointed

Termination of Received Packet

Packet Accepted

TL F 8582 – 10

to by the Current Page Register) The DMA then stores the

Receive Status a Pointer to where the next packet will be

stored (Buffer 4) and the number of received bytes Note

that the remaining bytes in the last buffer are discarded and

reception of the next packet begins on the next empty 256-

byte buffer boundary The Current Page Register is then

initialized to the next available buffer in the Buffer Ring (The

location of the next buffer had been previously calculated

and temporarily stored in an internal scratchpad register )

BUFFER RECOVERY FOR REJECTED PACKETS

If the packet is a runt packet or contains CRC or Frame

Alignment errors it is rejected The buffer management log-

ic resets the DMA back to the first buffer page used to store

the packet (pointed to by CURR) recovering all buffers that

had been used to store the rejected packet This operation

will not be performed if the NIC is programmed to accept

either runt packets or packets with CRC or Frame Alignment

errors The received CRC is always stored in buffer memory

after the last byte of received data for the packet

Termination of Received Packet

Packet Rejected

TL F 8582 – 13

Error Recovery

If the packet is rejected as shown the DMA is restored by

the NIC by reprogramming the DMA starting address point-

ed to by the Current Page Register

REMOVING PACKETS FROM THE RING

Packets are removed from the ring using the Remote DMA

or an external device When using the Remote DMA the

Send Packet command can be used This programs the Re-

mote DMA to automatically remove the received packet

pointed to by the Boundary Pointer At the end of the trans-

fer the NIC moves the Boundary Pointer freeing additional

buffers for reception The Boundary Pointer can also be

moved manually by programming the Boundary Register

Care should be taken to keep the Boundary Pointer at least

one buffer behind the Current Page Pointer

The following is a suggested method for maintaining the

Receive Buffer Ring pointers

1 At initialization set up a software variable (next

pkt) to

indicate where the next packet will be read At the begin-

ning of each Remote Read DMA operation the value of

pkt will be loaded into RSAR0 and RSAR1

2 When initializing the NIC set

BNDRY

PSTART

CURR

PSTART

pkt

PSTART

7 0 Packet Reception

(Continued)

3 After a packet is DMAed from the Receive Buffer Ring

the Next Page Pointer (second byte in NIC buffer header)

is used to update BNDRY and next

pkt

Next Page Pointer

BNDRY

Next Page Pointer

If BNDRY

PSTART then BNDRY

PSTOP

Note the size of the Receive Buffer Ring is reduced by one

256-byte buffer this will not however impede the operation

of the NIC

In StarLAN applications using bus clock frequencies greater

than 4 MHz the NIC does not update the buffer header

information properly because of the disparity between the

network and bus clock speeds The lower byte count is cop-

ied twice into the third and fourth locations of the buffer

header and the upper byte count is not written The upper

byte count however can be calculated from the current

next page pointer (second byte in the buffer header) and the

previous next page pointer (stored in memory by the CPU)

The following routine calculates the upper byte count and

allows StarLAN applications to be insensitive to bus clock

speeds Next

pkt is defined similarly as above

1st Received Packet Removed By Remote DMA

TL F 8582 – 57

upper byte count

next page pointer

pkt

if (upper byte count)

0 then

upper byte count

(PSTOP

pkt)

(next page pointer

PSTART)

if (lower byte count)

0 fch then

upper byte count

STORAGE FORMAT FOR RECEIVED PACKETS

The following diagrams describe the format for how re-

ceived packets are placed into memory by the local DMA

channel These modes are selected in the Data Configura-

tion Register

Storage Format

AD15

AD8

AD7

AD0

Next Packet

Receive

Pointer

Status

Receive

Byte Count 1

Byte Count 0

Byte 2

Byte 1

BOS

0 WTS

1 in Data Configuration Register

This format used with Series 32000 808X type processors

AD15

AD8

AD7

AD0

Next Packet

Receive

Pointer

Status

Receive

Byte Count 0

Byte Count 1

Byte 1

Byte 2

BOS

1 WTS

1 in Data Configuration Register

This format used with 68000 type processors

Note

The Receive Byte Count ordering remains the same for BOS

0 or 1

AD7

AD0

Receive Status

Next Packet

Pointer

Receive Byte

Count 0

Receive Byte

Count 1

Byte 0

Byte 1

BOS

0 WTS