fn3627

File Number

3627.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HSP48212

Digital Video Mixer

The Intersil HSP48212 is a 68 pin Digital Video Mixer IC

intended for use in multimedia and medical imaging

applications.

The HSP48212 allows the user to mix two video sources

based on a programmable weighting factor. After weighting

the input data signals, the Video Mixer simply adds the two

weighted signals mathematically. This results in the mixed

output, which is a weighted sum of the two sources.

The input and output interfaces are synchronous with respect

to the input clock, simplifying the user interface requirements.

Input Data (DINA, DINB), Mix Factor (M) and control signals

(RND, TCB) may be delayed relative to each other in order to

compensate for any misalignment that may have occurred

prior to entering the HSP48212. Each input’s delay may be

independently programmed up to seven clock cycles.

The output data may be rounded to 8, 10, 12, or 13-bits. The

enabling of data onto the output data bus is under the user’s

control via an output enable signal (OE).

Features

• 12-Bit Pixel Data

• Two’s Complement or Unsigned Data

• 12-Bit Mix Factor

• 13-Bit Signed or Unsigned Three State Output

• Overﬂow Detection and Output Saturation

• Rounding to 8, 10, 12, or 13-Bits

• Input and Output Pixel Data Synchronous to Clock

• Programmable Pipeline Delay of up to 7 Clock Cycles for

Control of Misaligned Input Data

• TTL Compatible Inputs/Outputs

• DC to 40MHz Clock Rate

Applications

• Video Summing (Frame Addition)

• Video Mixing

• Fade In/Out

• Video Switching

• High Speed Multiplying

Block Diagram

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HSP48212VC-40

0 to 70

64 Ld MQFP

Q64.14x14

HSP48212JC-40

0 to 70

68 Ld PLCC

N68.95

DINB0-11

1-M

DINA0-11

OUTPUT

FORMA

DOUT0-12

0-7

RND0-1

TCB

DELAY

0-7

DELAY

0-7

DELAY

0-7

DELAY

0-7

DELAY

SHIFT

LEFT

DOUT = 2 x [DINA x M + DINB x (1-M)]

Data Sheet

May 1999

Pinouts

64 LEAD MQFP

TOP VIEW

68 PIN PLCC

TOP VIEW

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

CLK

MIXEN

M10

M11

BYP

ASS

DINB11

DINB10

DINB9

GND

DINB8

DINB7

DINB6

DINB2

RND1

RND0

DELAY

DINB4

DINB3

DINB1

DINB0

DINA10

DINA11

DINA9

DINA8

DINA7

DINA6

DINA5

DINA4

DINA1

DINA3

DINA2

GND

DINA0

DINB5

DOUT12

DOUT11

DOUT10

DOUT9

GND

DOUT8

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

DOUT12

DOUT11

DOUT10

DOUT9

GND

DOUT8

DOUT7

N/C

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

CLK

MIXEN

N/C

M10

M11

BYP

ASS

DINB11

DINB10

DINB9

GND

DINB8

DINB7

DINB6

DINB2

RND1

RND0

DELAY

DINB4

DINB3

DINB1

DINB0

N/C

DINA10

DINA11

DINA9

DINA8

DINA7

DINA6

DINA5

DINA4

DINA1

DINA3

DINA2

GND

DINA0

N/C

DINB5

HSP48212

Pin Descriptions

NAME

PLCC PIN

TYPE

DESCRIPTION

CLK

Clock Input. All signal pins are synchronous with respect to this clock except LD, DEL, OE, and BY-

PASS.

DINA0-11

29-31

33-34

36-38

40-43

Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge

of CLK.

DINB0-11

10-15, 17

19-23

Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge

of CLK.

M0-11

62-65

67-68

2-7

Mix Input Bus. The range of M is from 0 to 1. The number format is unsigned, with one bit position

to the left of the binary point. If a value greater than 1 is placed on this bus, the internal circuitry will

saturate M to 1, i.e, anytime the MSB is 1, the internal value defaults to 1.00000000000; synchro-

nous to the rising edge of CLK.

Speciﬁes the number format of the input data busses DINA and DINB. 1 = unsigned, 0 = 2’s com-

plement. The signal has the same number of latency stages as the incoming data. Therefore, the

number format affects the incoming data but not the data in the internal pipeline stages. Synchro-

nous to the rising edge of CLK.

RND0-1

24-25

Speciﬁes the number of signiﬁcant bits on the output bus. 00 = 8-bit, 01 = 10-bit,

10 = 12-bit, 11 = 13-bit. Rounding is performed by adding a binary 1 to the bit position to the right of

the desired LSB. The remaining bits are forced to zero. These control signals have the same number

of latency stages as the incoming data. Therefore, the output round format does not take effect until

the current data has propagated to the output. Synchronous to the rising edge of CLK.

MIXEN

Mix Enable. This pin is used to disable the clock signal which samples the Mix input. When MIXEN

= 1, the M0-11 bus is sampled by the rising edge of CLK. When MIXEN = 0, the M0-11 bus is ignored

and the previously stored value of M0-11 is used. Synchronous to the rising edge of CLK.

Asynchronous Load Pin. LD is used to load the delay control registers. The delay control word is

loaded serially from LSB to MSB. This signal drives the clock input to a

15-bit serial shift register. Each LD cycle, the data is transferred through the register bank on the

rising edge of LD In order to load the delay control word, the user must supply exactly 15 LD pulses.

DEL

Delay Input. This is the serial input data that is sampled by the rising edge of LD. It is the input to the

ﬁrst stage of the 15-bit serial shift register which contains the delay control word. Synchronous to the

rising edge of LD.

BYPASS

Allows user to disable (bypass) the LD interface and use the default delay paths. When BYPASS =

1, the delay control word is forced to all 0’s and no extra delays are included in the paths. When BY-

PASS = 0, the delay control word must be initialized using the LD/DEL interface in order for the chip

to give predictable results. This pin is asynchronous and is not intended to change states during op-

eration.

DOUT0-12

59-56

54-53

51-50

48-44

Output Data Bus. The data on this bus reﬂects the results of the equation:

2x[AxM + Bx(1-M)]. The number format of the output is either 2’s complement or unsigned depend-

ing on the value of the TC signal during data input. The representation of DOUT is also dependent

on the value sampled on RND0-1 during data input.

(See RND0-1 and TC pin description).

Output Enable. Asynchronous input which takes effect immediately following a transition. When OE =

0 the DOUT bus is driving, when OE = 1 the DOUT bus is not driven (floating).

32, 49, 66

5V power supply. There are 3 V

pads.

GND

16, 39, 55

0V power supply. There are 3 GND pads.

HSP48212

Functional Description

The Digital Video Mixer is intended for use in professional

video, multimedia and medical imaging applications. The

HSP48212 allows the user to mix two video sources based

on a programmable weighting factor. After weighting the

input data signals, the Video Mixer simply adds the two

weighted signals mathematically. This results in the mixed

output, which is a weighted sum of the two sources. The

fundamental equation implemented by this architecture is:

where DINA and DINB are the two video sources (pixels)

and M is the weighting (Mix) factor. As expressed by this

equation, the output DOUT is a weighted average of the

incoming pixels. For instance, when M is set to 0 the DINB

input source is passed to the output, and when M is set to 1

the DINA input is passed to the output, and when M is set to

0.5 the output is the sum of the two sources DINA and DINB.

The user can therefore vary the mix factor to apply different

weights to each of the inputs DINA, DINB. This allows

functions such as fading in, fading out, fading between

images, graphics overlays, and keying. The multiplication

factor of 2 as seen in (EQ. 1) is accomplished through a 1-bit

shift left (See Figure 1). This shifter is not programmable and

cannot be accessed by the user.

The Functional Block Diagram is shown in Figure 1. It can be

seen that (EQ. 1) is directly implemented by this architecture.

The architecture has a 6 stage inherent latency. This

architecture is extremely flexible in that it allows the user to

account for misaligned input data by independently

programming up to seven additional delay stages for DINA0-

11, DINB0-11, and M0-11, as well as for the format control

signals TC and RND0-1. The programmable delay registers

are controlled by the signals DEL, LD, and BYPASS.

The HSP48212 input interface is primarily synchronous to the

rising edge of CLK with the exception of the programmable

delay control signals DEL, LD, and BYPASS. The output data

bus DOUT0-12 is registered synchronous to the rising edge of

CLK and may also be controlled via the asynchronous output

enable signal OE. The input data, DINA0-11 and DINB0-11,

as well as the mix factor M0-11 have 12-bit precision. The

output data DOUT0-12 has 13-bit precision to allow for 1-bit of

growth.

The signals TC and RND0-1 control the format of the input

and output data. TC allows DINA0-11 and DINB 0-11 to be

either two’s complement or unsigned (Note: DINA0-11 and

DINB0-11 must have the same format, i.e., no mixed mode).

The output data DOUT0-12 can be rounded to 8, 10, 12, or

13-bits as determined by the control signals RND0-1.

Input Data Format

DINA0-11 and DINB0-11 represent two digital video sources

(pixels). Each input bus has 12-bits of precision. They may

be represented in two’s complement form (TC = 0) or in

unsigned form (TC = 1). It is important to note that DINA0-11

and DINB0-11 must be represented in the same format (i.e.,

no mixed mode operation is allowed).

M0-11 supplies the weighting (Mix) factor and has 12-bits of

precision. M0-11 must be represented in unsigned format and

may range from 0 to 1. If a value greater than 1 is placed on the

bus, the internal circuitry will saturate M0-11 to 1.00000000000.

DINA0-11, DINB0-11, and M0-11 are synchronously

registered on the rising edge of CLK.

The signal MIXEN allows the user to disable the internal

clock signal which samples the M0-11 input bus. When

MIXEN = 0, the M0-11 bus is ignored and the previously

sampled M0-11 value is used. When MIXEN = 1, the M0-11

bus is sampled on the rising edge of CLK.

Programmable Delay

The input data (DINA0-11, DINB0-11), mix factor (M0-11),

and control signals (RND0-1, TC), may be delayed relative to

each other in order to compensate for any misalignment that

may have occurred prior to entering the HSP48212. Each

input’s delay may be independently programmed for up to

seven delays. In other words, the user can program a

different number of pipeline delays for each input. This

programmed delay is in addition to the inherent 6 stage

delay required by the architecture.

As shown in Figures 2 and 3, the programmable delay

information is loaded using the signals LD and DEL. LD is

the asynchronous load pin used to clock in the delay control

word. The delay control word is clocked into a 15-bit serial

shift register on the rising edge of LD (i.e., DEL is

synchronous to LD). The delay control word data is supplied

by the DEL signal beginning with the least signiﬁcant bit and

continuing until the most signiﬁcant bit has been clocked in.

On each LD cycle the DEL data input is transferred through

the register bank. The user must supply exactly 15 LD

pulses; if the shift register is clocked more than 15 times,

only the most recent 15 data inputs will be stored.

As previously stated, the length of the control word is 15-bits: 3-

bits are allocated for each of the 5 inputs, DINA0-11, DINB0-11,

M0-11, RND0-1, and TC. Each 3-bits of the control word allow

the user to specify from 0 to 7 additional delay stages by

programming the binary equivalent of the desired delay into the

appropriate bit position of the delay control word register (e.g.,

000 for 0 delays, 001 for 1 delay, ..., 111 for 7 delays).

DOUT = 2 x DINA x M + DINB x 1 -M

(

)

[

]

(EQ. 1)

HSP48212

The BYPASS control signal enables the programmable delay

registers to be bypassed. When BYPASS is high, the delay

control word is forced to all 0’s and no additional delays are

included in any of the input paths. However, when BYPASS

is low, the LD/DEL serial delay control word interface is

active and the delay control word must be initialized in order

to achieve any meaningful results.

Format Control Signals

The control signals TC and RND0-1 are used to specify the

input data representation and the output data representation

respectively. TC and RND0-1 are synchronous to CLK,

which allows them to be changed on a cycle by cycle basis if

needed. The control signals are designed to match the

latency of the data paths. When the control inputs change,

the new conﬁguration will effect the current input data and

will not effect the data in the pipeline stages. For example, if

the rounding selection is changed from 8-bit rounding to 10-

bit rounding on a given cycle, the output will remain in an 8-

bit representation while the new data is propagating through

the circuit. When the results of the new data are available at

the output, the number format will change to 10-bits.

The RND0-1 control signals determine the number of

signiﬁcant bits on the output bus DOUT0-12. The output

data may be rounded to 8, 10, 12, or 13-bits. The rounding

operation is performed by adding a binary 1 to the bit

position right of the desired LSB and forcing the undesired

bits to 0. For example, in 8-bit rounding, a 1 is added to the

9th bit to the right of the MSB (DOUT4), and DOUT0-4 are

forced to 0 (i.e., DOUT0-12 = XXXXXXXX00000).

Output Control

DOUT0-12 is the output data bus which represents the

weighted average of the incoming pixel data as indicated by

(EQ. 2):

The output data will be represented in either two’s

complement format or in unsigned format depending on the

value of the TC signal when the input data (DINA0-11 and

DINB0-11) is sampled by CLK. Similarly, the output

representation of DOUT0-12 is also dependent on the value

of RND0-1 during sampling of the input data.

The output data DOUT0-12 is registered at the output of the

HSP48212 on the rising edge of CLK. The output data may

be accessed through the activation of the signal OE. OE is

an asynchronous input which, when low, causes the

DOUT0-12 bus to drive; when OE is high, the DOUT0-12

bus is not driven (ﬂoating).

TABLE 1.

INPUT SIGNAL

CONTROL WORD BIT POSITION

RND0-1

12-14

9-11

M0-11

6-8y

DINB0-11

3-5

DINA0-11

0-2

D10

D11

D12

D13

D14

DEL

FIGURE 2. DELAY CONTROL WORD SHIFT REGISTER

DOUT = 2 x

DINA x M

(

)

+ DINB x 1 - M

(

)

(

)

[

]

(EQ. 2)

D14

D13

D12

D11

D10

DINA

DELAY

DINB

DELAY

MIX

DELAY

RND

DELAY

DEL

FIGURE 3. DELAY CONTROL WORD TIMING DIAGRAM

HSP48212

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V

+0.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65

C to 150

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . .300

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range, Commercial . . . . . . . . . . . . . . . . .5V

Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . . 0

C to 70

Thermal Resistance (Typical, Note 1)

(

C/W)

PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

Power Supply Current

CCOP

= Max, CLK Frequency 40MHz,

(Notes 3, 4)

170

Standby Power Supply Current

CCSB

= Max, Outputs Not Loaded

500

Input Leakage Current

= Max, Input = 0V or V

-10

Output Leakage Current

= Max, Input = 0V or V

-10

Logical One Input Voltage

= Max

2.0

Logical Zero Input Voltage

= Min

0.8

Logical One Output Voltage

= -400

A, V

= Min

2.6

Logical Zero Output Voltage

= 2mA, V

= Min

0.4

Clock Input High

IHC

= Max

3.0

Clock input Low

ILC

= Min

0.8

Input Capacitance

CLK Frequency 1MHz, all measurements

referenced to GND.

= 25

C, Note 2

Output Capacitance

OUT

NOTES:

2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.

3. Power Supply current is proportional to operating frequency. Typical rating for I

CCOP

is 4.25mA/MHz.

4. Output load per test load circuit and C

= 40pF.

AC Electrical Speciﬁcations

PARAMETER

SYMBOL

40MHz

UNITS

MIN

MAX

CLK Period

CLK High

CLK Low

LD Period

LD High

LD Low

Data Setup Time to CLK High

Data Hold Time from CLK High

HSP48212

AC Test Load Circuit

MIX Data Setup Time to CLK High

MIX Data Hold Time From CLK High

Control Data Setup Time to CLK High

Control Data Hold Time From CLK High

DEL Setup to LD High

DLS

DEL Hold from LD High

DLH

CLK to Output Data Delay

OUT

Output Enable Time

Output Disable Time

ns, Note 6

Output Rise/Fall Time

ns. Note 6

NOTES:

5. AC tests performed with C

= 40pF, I

= 2mA, and I

= -400

A. Input reference level CLK = 2.0V. Input reference level for all other inputs is

1.5V. Test V

= 3.0V, V

IHC

= 4.0V, V

= 0V, V

ILC

= 0V.

6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or Design

changes.

AC Electrical Speciﬁcations

(Continued)

PARAMETER

SYMBOL

40MHz

UNITS

MIN

MAX

EQUIVALENT CIRCUIT

(NOTE 7) C

IOH

1.5V

IOL

DUT

SWITCH S1 OPEN FOR

CCSB

AND I

CCOP

NOTE:

7. Test Head Capacitance.

HSP48212