1
ICL7106, ICL7107,
ICL7106S, ICL7107S
3
1
/
2
Digit,
LCD/LED Display, A/D Converters
January 1998
Features
• Guaranteed Zero Reading for 0V Input on All Scales
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• True Differential Input and Reference, Direct Display Drive
- LCD ICL7106, LED lCL7107
• Low Noise - Less Than 15
µ
V
P-P
• On Chip Clock and Reference
• Low Power Dissipation - Typically Less Than 10mW
• No Additional Active Circuits Required
• Enhanced Display Stability (ICL7106S, ICL7107S)
Description
The Intersil ICL7106 and ICL7107 are high performance, low
power, 3
1
/
2
digit A/D converters. Included are seven seg-
ment decoders, display drivers, a reference, and a clock.
The ICL7106 is designed to interface with a liquid crystal dis-
play (LCD) and includes a multiplexed backplane drive; the
ICL7107 will directly drive an instrument size light emitting
diode (LED) display.
The ICL7106 and ICL7107 bring together a combination of
high accuracy, versatility, and true economy. It features auto-
zero to less than 10
µ
V, zero drift of less than 1
µ
V/
o
C, input
bias current of 10pA (Max), and rollover error of less than
one count. True differential inputs and reference are useful in
all systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
type transducers. Finally, the true economy of single power
supply operation (ICL7106), enables a high performance
panel meter to be built with the addition of only 10 passive
components and a display.
Ordering Information
PART NO.
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
ICL7106CPL
0 to 70
40 Ld PDIP
E40.6
ICL7106RCPL
0 to 70
40 Ld PDIP (Note)
E40.6
ICL7106CM44
0 to 70
44 Ld MQFP
Q44.10x10
ICL7106SCPL
0 to 70
40 Ld PDIP
E40.6
ICL7107SCPL
0 to 70
40 Ld PDIP
E40.6
ICL7107CPL
0 to 70
40 Ld PDIP
E40.6
ICL7107RCPL
0 to 70
40 Ld PDIP (Note)
E40.6
ICL7107CM44
0 to 70
44 Ld MQFP
Q44.10x10
NOTE: “R” indicates device with reversed leads for mounting to PC
board underside. “S” indicates enhanced stability.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
3082.2
2
Pinouts
ICL7106, ICL7107 (PDIP)
TOP VIEW
ICL7106R, ICL7107R (PDIP)
TOP VIEW
ICL7106, ICL7107 (MQFP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10’s)
C3
A3
G3
BP/GND
(1’s)
(10’s)
(100’s)
(MINUS)
(100’s)
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10’s)
C3
A3
G3
BP/GND
(1’s)
(10’s)
(100’s)
(MINUS)
(100’s)
OSC 2
NC
OSC 3
TEST
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 1
V+
D1
C1
B1
A1 F1 G1 E1 D2 C2
28
27
26
25
24
23
22
21
20
19
18
B2 A2 F2 E2 D3
B3
F3
E3
AB4
POL
BP/GND
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
A-Z
B
UFF
INT
V-
NC
G2
C3
A3
G3
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
ICL7106, ICL7107, ICL7106S, ICL7107S
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage
ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-
Clock Input
ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to
±
100
µ
A.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Zero Input Reading
V
IN
= 0.0V, Full Scale = 200mV
-000.0
±
000.0
+000.0
Digital
Reading
Stability (Last Digit) (ICL7106S, ICL7107S
Only)
Fixed Input Voltage (Note 7)
-000.0
±
000.0
+000.0
Digital
Reading
Ratiometric Reading
V
lN
= V
REF
, V
REF
= 100mV
999
999/10
00
1000
Digital
Reading
Rollover Error
-V
IN
= +V
lN
≅
200mV
Difference in Reading for Equal Positive and
Negative Inputs Near Full Scale
-
±
0.2
±
1
Counts
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 6)
-
±
0.2
±
1
Counts
Common Mode Rejection Ratio
V
CM
= 1V, V
IN
= 0V, Full Scale = 200mV (Note 6)
-
50
-
µ
V/V
Noise
V
IN
= 0V, Full Scale = 200mV
(Peak-To-Peak Value Not Exceeded 95% of Time)
-
15
-
µ
V
Leakage Current Input
V
lN
= 0 (Note 6)
-
1
10
pA
Zero Reading Drift
V
lN
= 0, 0
o
C To 70
o
C (Note 6)
-
0.2
1
µ
V/
o
C
Scale Factor Temperature Coefficient
V
IN
= 199mV, 0
o
C To 70
o
C
,
(Ext. Ref. 0ppm/
o
C) (Note 6)
-
1
5
ppm/
o
C
End Power Supply Character V+ Supply
Current
V
IN
= 0 (Does Not Include LED Current for ICL7107)
-
1.0
1.8
mA
End Power Supply Character V- Supply Current
ICL7107 Only
-
0.6
1.8
mA
COMMON Pin Analog Common Voltage
25k
Ω
Between Common and
Positive Supply (With Respect to + Supply)
2.4
3.0
3.2
V
Temperature Coefficient of Analog Common
25k
Ω
Between Common and
Positive Supply (With Respect to + Supply)
-
80
-
ppm/
o
C
DISPLAY DRIVER ICL7106 ONLY
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V (Note 5)
4
5.5
6
V
ICL7106, ICL7107, ICL7106S, ICL7107S
4
Typical Applications and Test Circuits
DISPLAY DRIVER ICL7107 ONLY
Segment Sinking Current
V+ = 5V, Segment Voltage = 3V
(Except Pins 19 and 20)
5
8
-
mA
Pin 19 Only
10
16
-
mA
Pin 20 Only
4
7
-
mA
NOTES:
3. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
4. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at T
A
= 25
o
C, fCLOCK = 48kHz. ICL7106 is tested in the
circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2.
5. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
6. Not tested, guaranteed by design.
7. Sample Tested.
Electrical Specifications
(Note 3) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COM
IN HI
IN LO
A-Z
B
UFF
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
9V
ICL7106
C
1
= 0.1
µ
F
C
2
= 0.47
µ
F
C
3
= 0.22
µ
F
C
4
= 100pF
C
5
= 0.02
µ
F
R
1
= 24k
Ω
R
2
= 47k
Ω
R
3
= 100k
Ω
R
4
= 1k
Ω
R
5
= 1M
Ω
+
-
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COM
IN HI
IN LO
A-Z
B
UFF
INT
V-
G2
C3
A3
G3
GND
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
ICL7107
+5V
-5V
C
1
= 0.1
µ
F
C
2
= 0.47
µ
F
C
3
= 0.22
µ
F
C
4
= 100pF
C
5
= 0.02
µ
F
R
1
= 24k
Ω
R
2
= 47k
Ω
R
3
= 100k
Ω
R
4
= 1k
Ω
R
5
= 1M
Ω
ICL7106, ICL7107, ICL7106S, ICL7107S
5
Typical Integrator Amplifier Output Waveform (INT Pin)
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
f
OSC
= 0.45/RC
C
OSC
> 50pF; R
OSC
> 50k
Ω
f
OSC
(Typ) = 48kHz
• OSCILLATOR PERIOD
t
OSC
= RC/0.45
• INTEGRATION CLOCK FREQUENCY
f
CLOCK
= f
OSC
/4
• INTEGRATION PERIOD
t
INT
= 1000 x (4/f
OSC
)
• 60/50Hz REJECTION CRITERION
t
INT
/t
60Hz
or t
lNT
/t
60Hz
= Integer
• OPTIMUM INTEGRATION CURRENT
I
INT
= 4
µ
A
• FULL SCALE ANALOG INPUT VOLTAGE
V
lNFS
(Typ) = 200mV or 2V
• INTEGRATE RESISTOR
• INTEGRATE CAPACITOR
• INTEGRATOR OUTPUT VOLTAGE SWING
• V
INT
MAXIMUM SWING:
(V- + 0.5V) < V
INT
< (V+ - 0.5V), V
INT
(Typ) = 2V
• DISPLAY COUNT
• CONVERSION CYCLE
t
CYC
= t
CL0CK
x 4000
t
CYC
= t
OSC
x 16,000
when f
OSC
= 48kHz; t
CYC
= 333ms
• COMMON MODE INPUT VOLTAGE
(V- + 1V) < V
lN
< (V+ - 0.5V)
• AUTO-ZERO CAPACITOR
0.01
µ
F < C
AZ
< 1
µ
F
• REFERENCE CAPACITOR
0.1
µ
F < C
REF
< 1
µ
F
• V
COM
Biased between Vi and V-.
• V
COM
≅
V+ - 2.8V
Regulation lost when V+ to V- <
≅
6.8V
If V
COM
is externally pulled down to (V+ to V-)/2,
the V
COM
circuit will turn off.
• ICL7106 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
V
GND
≅
V+ - 4.5V
• ICL7106 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude.
• ICL7107 POWER SUPPLY: DUAL
±
5.0V
V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND
• ICL7107 DISPLAY: LED
Type: Non-Multiplexed Common Anode
R
INT
V
INFS
I
INT
-----------------
=
C
INT
t
INT
(
)
I
INT
(
)
V
INT
--------------------------------
=
V
INT
t
INT
(
)
I
INT
(
)
C
INT
--------------------------------
=
COUNT
1000
V
IN
V
REF
---------------
×
=
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x t
CLOCK
= 16,000 x t
OSC
ICL7106, ICL7107, ICL7106S, ICL7107S
6
Detailed Description
Analog Section
Figure 3 shows the Analog Section for the ICL7106 and
ICL7107. Each measurement cycle is divided into three
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C
AZ
to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10
µ
V.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative sup-
ply. In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator out-
put does not saturate. A worst case condition would be a large
positive common mode voltage with a near full scale negative
differential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common mode voltage. For these critical appli-
cations the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of
accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.
DISPLAY COUNT = 1000
V
IN