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3-10
April 1997
HMA510/883
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- I
CCSB
= 500
µ
A Maximum
- I
CCOP
= 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• Three-State Outputs
Description
The HMA510/883 is a high speed, low power CMOS 16 x
16-bit parallel multiplier accumulator capable of operating at
55ns clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HMA510GM-55/883
-55 to 125
68 Ld CPGA
G68.B
HMA510GM-65/883
-55 to 125
68 Ld CPGA
G68.B
HMA510GM-75/883
-55 to 125
68 Ld CPGA
G68.B
REGISTER
SUB
ACC
RND
TC
Y0-15 P0-15
16
16
X0-15
CLKY
CLKX
ACCUMULATOR
XTP REGISTER
MSP REGISTER
LSP REGISTER
PRELOAD
CLKP
3
16
35
MULTIPLIER ARRAY
35
P32-34
16
P16-31
OEX
OEM
OEL
REGISTER
REGISTER
File Number
2807.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
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3-11
Pinout
68 LEAD CPGA
TOP VIEW
Pin Descriptions
NAME
TYPE
DESCRIPTION
V
CC
The +5V power supply pins. 0.1
µ
F capacitors between the V
CC
and GND pins are recommended.
GND
The device ground.
X0-X15
I
X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or
unsigned magnitude format.
Y0-Y15/P0-P15
I/O
Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's com-
plement or unsigned magnitude format. It may also be used for output of the least significant product
(P0-P15) or for preloading the LSP Register.
P16-P3
I/O
MSP Output Data. This 16-bit port is used to provide the most significant product output (P16-P31).
It may also be used to preload the MSP Register.
P32-P34
I/O
XTP Output Data. This 3-bit port is used to provide the extended product output (P32-P34). It may
also be used to preload the XTP Register.
TC
I
Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH.
A LOW indicates the data is to be interpreted as unsigned magnitude format. This control is latched
on the rising edge of CLKX or CLKY.
ACC
I
Accumulate Control. When this control is HIGH, the Accumulator Output Register contents are added
to or subtracted from the current product, and the result is stored back into the Accumulator Output
Register.
When LOW, the product is loaded into the Accumulator Output Register overwriting the current con-
tents. This control is also latched on the rising edge of CLKX or CLKY.
11
10
9
8
7
6
5
4
3
2
1
N/C
X14
X12
X10
X8
X6
X4
X2
X0
Y1/P1
Y2/P2
X13
X11
X9
X7
X5
X3
X1
Y0/P0
N/C
P33
P32
P30
P28
P26
P24
P22
P20
P18
P16
N/C
N/C
P31
P29
P27
P25
P23
P21
P19
P17
X15
OEL
Y3/P3
Y4/P4
RND
SUB
Y5/P5
Y6/P6
ACC
CLKX
Y7/P7
GND
CLKY
V
CC
Y8/P8
Y9/P9
TC
OEX
Y10/
Y11/
PREL
OEM
Y12/
Y13/
CLKP
P34
Y14/
Y15/
B
A
K
L
C
D
E
F
G
H
J
P10
P12
P14
P11
P13
P15
TOP VIEW
HMA510/883
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3-12
SUB
I
Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are sub-
tracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register
contents and the current product are summed. The SUB control input is latched on the rising edge of
CLKX or CLKY.
RND
I
Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When
LOW, the product is unchanged.
PREL
I
Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the
Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will
be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers func-
tion in a normal manner.
OEL
I
Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL
is LOW, the port is enabled for LSP output.
OEM
I
MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP Register.
OEX
I
XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for pre-
loading the XTP Register.
CLKX
I
X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKY
I
Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKP
I
Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the
preload control is active, the data on the I/O ports is loaded into these registers. If preload is not ac-
tive, the accumulated product is loaded into the registers.
Pin Descriptions
(Continued)
NAME
TYPE
DESCRIPTION
HMA510/883
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3-13
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input or Output Voltage Applied . . . . . . . . G ND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 55
o
C to 125
o
C
Thermal Resistance (Typical, Note 1)
θ
JA (
o
C/W)
θ
JC (
o
C/W)
CPGA Package . . . . . . . . . . . . . . . . . .
43
10
Maximum Package Power Dissipation at 125
o
C
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.17W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . . 65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4800 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. HMA5lO/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
TEST CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE (
o
C)
MIN
MAX
UNITS
Logical One Input
Voltage
V
lH
V
CC
= 5.5V
1, 2, 3
-55
≤
T
A
≤
125
2.2
-
V
Logical Zero Input
Voltage
V
IL
V
CC
= 4.5V
1, 2, 3
-55
≤
T
A
≤
125
-
0.8
V
Output HIGH Voltage
V
OH
I
OH
= -400
µ
A
V
CC
= 4.5V (Note 2)
1, 2, 3
-55
≤
T
A
≤
125
2.6
-
V
Output LOW Voltage
V
OL
I
OL
= +4.0mA
V
CC
= 4.5V (Note 2)
1, 2, 3
-55
≤
T
A
≤
125
-
0.4
V
Input Leakage Current
I
I
V
lN
= V
CC
or GND
1, 2, 3
-55
≤
T
A
≤
125
-10
+10
µ
A
Output or I/O Leakage
Current
I
O
V
OUT
= V
CC
or GND,
V
CC
= 5.5V
1, 2, 3
-55
≤
T
A
≤
125
-10
+10
µ
A
Standby Power Supply
Current
I
CCSB
V
IN
= V
CC
or GND,
V
CC
= 5.5V,
Outputs Open
1, 2, 3
-55
≤
T
A
≤
125
-
500
µ
A
Operating Power Supply
Current
I
CCOP
f = 1.0MHz, V
IN
= V
CC
or GND V
CC
= 5.5V
(Note 3)
1, 2, 3
-55
≤
T
A
≤
125
-
7.0
mA
Functional Test
FT
(Note 4)
7, 8
-55
≤
T
A
≤
125
-
-
NOTES:
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current a proportional to frequency, typical rating is 5mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
(clock inputs) = 3.2V, V
lH
(all other inputs) = 2.6V, V
IL
= 0.4V, V
OH
≥
1.5V, and V
OL
≤
1.5V.
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 5)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE (
o
C)
-55
-65
-75
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Multiply Accumu-
late Time
t
MA
9, 10, 11
-55
≤
T
A
≤
125
-
55
-
65
-
75
ns
Input Setup Time
t
S
9, 10, 11
-55
≤
T
A
≤
125
20
-
25
-
25
-
ns
HMA510/883
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3-14
Clock HIGH
Pulse Width
t
PWH
9, 10, 11
-55
≤
T
A
≤
125
20
-
25
-
25
-
ns
Clock LOW
Pulse Width
t
PWL
9, 10, 11
-55
≤
T
A
≤
125
20
-
25
-
25
-
ns
Output Delay
t
D
9, 10, 11
-55
≤
T
A
≤
125
-
30
-
35
-
35
ns
Three-State
Enable Time
t
ENA
(Note 5)
9, 10, 11
-55
≤
T
A
≤
125
-
30
-
30
-
35
ns
NOTES:
5. AC Testing as follows: V
CC
= 4.5V and 5.5V. Input levels 0V and 3.0V (0V and 3.2V tor clock inputs). Timing reference levels = 1.5V,
Output load per test load circuit, with V
1
= 2.4V, R
1
= 500
Ω
and C
L
= 40pF.
6. Transition is measured at 1200mV from steady state voltage, Output loading per test load circuit, with V
1
= 1.5V, R
1
= 500
Ω
and C
L
=
40pF.
TABLE 3. HMA510/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
TEST
CONDITIONS
NOTE
TEMPERATURE (
o
C)
-55
-65
-75
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
lnput Capacitance
C
IN
V
CC
= Open,
f = 1MHz All mea-
surements are ref-
erenced to device
GND
1
T
A
= 25
-
10
-
10
-
10
pF
Output Capacitance
C
OUT
1
T
A
= 25
-
10
-
10
-
10
pF
I/O Capacitance
C
I/O
1
T
A
= 25
-
15
-
15
-
15
pF
Input Hold Time
t
H
1
-55
≤
T
A
≤
125
3
-
3
-
3
-
ns
Three-State Disable
Time
t
DIS
1
-55
≤
T
A
≤
125
-
30
-
30
-
30
ns
Output Rise Time
t
r
From 0.8V to 2.0V
1
-55
≤
T
A
≤
125
-
10
-
10
-
10
ns
Output Fall Time
t
f
From 2.0V to 0.8V
1
-55
≤
T
A
≤
125
-
10
-
10
-
10
ns
NOTE:
7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10,11
Group A
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C and D
Samples/5005
1, 7, 9
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 5)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE (
o
C)
-55
-65
-75
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
HMA510/883
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3-15
AC Test Circuit
NOTE: Includes Stray and Jig Capacitance
AC Testing Input, Output Waveforms
NOTE: AC Testing: All Parameters tested as per test circuit. Input
rise and fall times are driven at 1ns/V.
DUT
C
1
(SEE NOTE)
V
1
R
1
V
IH
V
IL
V
OH
V
OL
1.5V
1.5V
Timing Diagram
FIGURE 1. SET-UP AND HOLD TIME
FIGURE 2. THREE-STATE CONTROL
FIGURE 3. HMA510 TIMING DIAGRAM
FIGURE 4. PRELOAD TIMING DIAGRAM
DATA
INPUT
CLOCK
INPUT
3.0V
1.5V
0V
3.0V
1.5V
0V
t
S
t
H
THREE
STATE
CONTROL
t
DIS
t
ENA
1.5V
OUTPUT
STATE
HIGH IMPEDANCE
THREE
CLKX
XIN, YIN
t
PWL
t
PWH
t
HCL
t
H
t
S
t
MA
t
D
RND, TC
ACC, SUB
CLKP
OUTPUT P, Y
CLKY
t
PWH
t
PWL
CLKP
PREL
OEX
OEM
OEL
OUTPUT
PINS
t
S
t
H
HMA510/883
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3-16
Burn-In Circuit
68 LEAD CPGA
TOP VIEW
11
10
9
8
7
6
5
4
3
2
1
N/C
X14
X12
X10
X8
X6
X4
X2
X0
Y1/P1
Y2/P2
X13
X11
X9
X7
X5
X3
X1
Y0/P0
N/C
P33
P32
P30
P28
P26
P24
P22
P20
P18
P16
N/C
N/C
P31
P29
P27
P25
P23
P21
P19
P17
X15
OEL
Y3/P3
Y4/P4
RND
SUB
Y5/P5
Y6/P6
ACC
CLKX
Y7/P7
GND
CLKY
V
CC
Y8/P8
Y9/P9
TC
OEX
Y10/
Y11/
PREL
OEM
Y12/
Y13/
CLKP
P34
Y14/
Y15/
B
A
K
L
C
D
E
F
G
H
J
P10
P12
P14
P11
P13
P15
CPGA PIN
PIN NAME
BURN-IN SIGNAL
B6
X6
F1
A6
X5
F2
B5
X4
F3
A5
X3
F4
B4
X2
F5
A4
X1
F6
B3
X0
F7
A3
Y0/P0
F8
B2
Y1/P1
F9
B1
Y2/P2
F10
C2
Y3/P3
F11
C1
Y4/P4
F12
D2
Y5/P5
F13
D1
Y6/P6
F14
E2
Y7/P7
F15
E1
GND
GND
F2
Y8/P8
F1
F1
Y9/P9
F2
G2
Y10/P10
F3
G1
Y11/P11
F5
H2
Y12/P12
F4
H1
Y13/P13
F4
J2
Y14/P14
F8
J1
Y15/P15
F9
K2
P16
V
CC
/2
L2
P17
V
CC
/2
K3
P18
V
CC
/2
L3
P19
V
CC
/2
K4
P20
V
CC
/2
L4
P21
V
CC
/2
K5
P22
V
CC
/2
L5
P23
V
CC
/2
K6
P24
V
CC
/2
L6