1K (64 X 16) SERIAL MICROWIRE EEPROM

ST93CS46

ST93CS47

1K (64 x 16) SERIAL MICROWIRE EEPROM

NOT FOR NEW DESIGN

June 1997

1/16

This is information on a product still in production bu t not recommended for new de signs.

AI00884B

VCC

ST93CS46

ST93CS47

VSS

PRE

Figure 1. Logic Diagram

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

SELF-TIMED PROGRAMMING CYCLE with

AUTO-ERASE

READY/BUSY SIGNAL DURING

PROGRAMMING

SINGLE SUPPLY VOLTAGE

– 3V to 5.5V for the ST93CS46

– 2.5V to 5.5V for the ST93CS47

USER DEFINED WRITE PROTECTED AREA

PAGE WRITE MODE (4 WORDS)

SEQUENTIAL READ OPERATION

5ms TYPICAL PROGRAMMING TIME

ST93CS46 and ST93CS47 are replaced by

the M93S46

DESCRIPTION

The ST93CS46 and ST93CS47 are 1K bit Electri-

cally Erasable Programmable Memory (EEPROM)

fabricated with SGS-THOMSON’s High Endurance

Single Polysilicon CMOS technology. The memory

is accessed through a serial input D and output Q.

The 1K bit memory is organized as 64 x 16 bit

words.The memory is accessed by a set of instruc-

tions which include Read, Write, Page Write, Write

All and instructions used to set the memory protec-

tion. A Read instruction loads the address of the

first word to be read into an internal address

pointer.

Chip Select Input

Serial Data Input

Serial Data Output

Serial Clock

PRE

Protect Enable

Write Enable

Supply Voltage

Ground

Table 1. Signal Names

SO8 (M)

150mil Width

PSDIP8 (B)

0.4mm Frame

DESCRIPTION (cont’d)

The data is then clocked out serially. The address

pointer is automatically incremented after the data

is output and, if the Chip Select input (S) is held

High, the ST93CS46/47 can output a sequential

stream of data words. In this way, the memory can

be read as a data stream of 16 to 1024 bits, or

continuously as the address counter automatically

rolls over to 00 when the highest address is

reached. Within the time required by a program-

ming cycle (t

), up to 4 words may be written with

the help of the Page Write instruction; the whole

memory may also be erased, or set to a predeter-

mined pattern, by using the Write All instruction.

Within the memory, an user defined area may be

protected against further Write instructions. The

size of this area is defined by the content of a

VSS

PRE

VCC

AI00885B

ST93CS46

ST93CS47

Figure 2A. DIP Pin Connections

VSS

PRE

VCC

AI00886C

ST93CS46

ST93CS47

Figure 2B. SO Pin Connections

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

–40 to 85

STG

Storage Temperature

–65 to 150

LEAD

Lead Temperature, Soldering

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

215

260

Input or Output Voltages (Q = V

or Hi-Z)

–0.3 to V

+0.5

Supply Voltage

–0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

3000

Electrostatic Discharge Voltage (Machine model)

(3)

500

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

Ω

3. EIAJ IC-121 (Condition C) (200pF, 0

Ω

Table 2. Absolute Maximum Ratings

(1)

Protect Register, located outside of the memory

array. As a final protection step, data may be per-

manently protected by programming a One Time

Programing bit (OTP bit) which locks the Protect

Programming is internally self-timed (the external

clock signal on C input may be disconnected or left

running after the start of a Write cycle) and does

not require an erase cycle prior to the Write instruc-

tion. The Write instruction writes 16 bits at one time

into one of the 64 words, the Page Write instruction

writes up to 4 words of 16 bits to sequential loca-

tions, assuming in both cases that all addresses

are outside the Write Protected area.

After the start of the programming cycle, a

Ready/Busy signal is available on the Data output

(Q) when the Chip Select (S) input pin is driven

High.

2/16

ST93CS46, ST93CS47

Input Rise and Fall Times

≤

20ns (10% to 90%)

Input Pulse Voltages

0.4V to 2.4V

Input and Output Timing

Reference Voltages

0.8 and 2V

AC MEASUREMENT CONDITIONS

Note that Output Hi-Z is defined as the point where data

is no longer driven.

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Figure 3. AC Testing Input Output Waveforms

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Note: 1. Sampled only, not 100% tested.

Table 3. Capacitance

(1)

= 25

C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

≤

2.5

Output Leakage Current

≤

OUT

≤

Q in Hi-Z

2.5

Supply Current (TTL Inputs)

S = V

, f = 1 MHz

Supply Current (CMOS Inputs)

S = V

, f = 1 MHz

CC1

Supply Current (Standby)

S = V

, C = V

Input Low Voltage (ST93CS46,47)

4.5V

≤

5.5V

–0.1

0.8

Input Low Voltage (ST93CS46)

≤

5.5V

–0.1

0.2 V

Input Low Voltage (ST93CS47)

2.5V

≤

5.5V

–0.1

0.2 V

Input High Voltage (ST93CS46,47)

4.5V

≤

5.5V

+ 1

Input High Voltage (ST93CS46)

≤

5.5V

0.8 V

+ 1

Input High Voltage (ST93CS47)

2.5V

≤

5.5V

0.8 V

+ 1

Output Low Voltage

= 2.1mA

0.4

= 10

0.2

Output High Voltage

= –400

2.4

= –10

– 0.2

Table 4. DC Characteristics (T

= 0 to 70

C or –40 to 85

C; V

= 3V to 5.5V for ST93CS46 and

= 2.5V to 5.5V for ST93CS47)

3/16

ST93CS46, ST93CS47

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

PRVCH

PRES

Protect Enable Valid to Clock High

WVCH

PES

Write Enable Valid to Clock High

SHCH

CSS

Chip Select High to Clock High

DVCH

DIS

Input Valid to Clock High

100

CHDX

DIH

Clock High to Input Transition

100

CHQL

PD0

Clock High to Output Low

500

CHQV

PD1

Clock High to Output Valid

500

CLPRX

PREH

Clock Low to Protect Enable Transition

SLWX

PEH

Chip Select Low to Write Enable Transition

250

CLSL

CSH

Clock Low to Chip Select Transition

SLSH

Chip Select Low to Chip Select High

Note 1

250

SHQV

Chip Select High to Output Valid

500

SLQZ

Chip Select Low to Output Hi-Z

300

CHCL

SKH

Clock High to Clock Low

Note 2

250

CLCH

SKL

Clock Low to Clock High

Note 2

250

Erase/Write Cycle time

Clock Frequency

MHz

Notes: 1. Chip Select must be brought low for a minimum of 250 ns (t

SLSH

) between consecutive instruction cycles.

2. The Clock frequency specification calls for a minimum clock period of 1

s, therefore the sum of the timings t

CHCL

+ t

CLCH

must be greater or equal to 1

s. For example, if t

CHCL

is 250 ns, then t

CLCH

must be at least 750 ns.

Table 5. DC Characteristics (T

= 0 to 70

C or –40 to 85

C; V

= 3V to 5.5V for ST93CS46 and

= 2.5V to 5.5V for ST93CS47)

PRE

OP CODE

START

OP CODE INPUT

tCHDX

tDVCH

tSHCH

tCLCH

tCHCL

tWVCH

tPRVCH

AI00887

Figure 4. Synchronous Timing, Start and Op-Code Input

4/16

ST93CS46, ST93CS47

POWER-ON DATA PROTECTION

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit resets all internal programming

circuitry and sets the device in the Write Disable

mode. When V

reaches its functional value, the

device is properlyreset (in the Write Disable mode)

and is ready to decode and execute an incoming

instruction. A stable V

must be applied before

any logic signal.

INSTRUCTIONS

The ST93CS46/47 has eleven instructions, as

shown in Table 6. Each instruction is preceded by

the rising edge of the signal applied on the Chip

Select (S) input (assuming that the Clock C is low),

followed by a ’1’ read on D input during the rising

edge of the clock C. The op-codes of the instruc-

tions are made up of the 2 following bits. Some

instructions use only these first two bits, others use

also the first two bits of the address field to define

the op-code. The address field is six bits long

(A5-A0).

The ST93CS46/47 is fabricated in CMOS technol-

ogy and is therefore able to run from zero Hz (static

input signals) up to the maximum ratings (specified

in Table 5).

Read

The Read instruction (READ) outputs serial data

on the Data Output (Q). When a READ instruction

is received, the instruction and address are de-

coded and the data from the memory is transferred

into an output shiftregister. A dummy ’0’ bit is output

first followed by the 16 bit word with the MSB first.

Instruction

Description

Pin

(1)

PRE

Pin

Code

Address

(1)

Data

Additional

Information

READ

Read Data from Memory

’0’

A5-A0

Q15-Q0

WRITE

Write Data to Memory

’1’

’0’

A5-A0

D15-D0

Write is executed if

the address is not

inside the Protected

area

PAWRITE

Page Write to Memory

’1’

’0’

A5-A0

D15-D0

Write is executed if

all the addresses

are not inside the

Protected area

WRALL

Write All Memory

’1’

’0’

01XXXX

D15-D0

Write all data if the

Protect Register is

cleared

WEN

Write Enable

’1’

’0’

11XXXX

WDS

Write Disable

’0’

00XXXX

PRREAD

Protect Register Read

’1’

XXXXXX

Q8-Q0

Data Output =

Protect Register

content + Protect

Flag bit

PRWRITE

Protect Register Write

’1’

A5-A0

Data above

specified address

A5-A0 are protected

PRCLEAR

Protect Register Clear

’1’

111111

Protect Flag is also

cleared (cleared

Flag = 1)

PREN

Protect Register Enable

’1’

11XXXX

PRDS

Protect Register Disable

’1’

000000

OTP bit is set

permanently

Note: 1. X = don’t care bit.

Table 6. Instruction Set

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ST93CS46, ST93CS47

Output data changes are triggered by the Low to

High transition of the Clock (C). The ST93CS46/47

will automatically increment the address and will

clock out the next word as long as the Chip Select

input (S) is held High. In this case the dummy ’0’ bit

is NOT output between words and a continuous

stream of data can be read.

Write Enable and Write Disable

The Write Enable instruction (WEN) authorizes the

following Write instructions to be executed, the

Write Disable instruction (WDS) disables the exe-

cution of the following Erase/Write instructions.

When power is first applied, the ST93CS46/47

enters the Disable mode. When the Write Enable

instruction (WEN) is executed, Write instructions

remain enabled until a Write Disable instruction

(WDS) is executed or if the Power-on reset circuit

becomes active due to a reduced V

. To protect

the memory contents from accidental corruption, it

is advisable to issue the WDS instruction after

every write cycle.

The READ instruction is not affected by the WEN

or WDS instructions.

Write

The Write instruction (WRITE) is followed by the

address and the word to be written. The Write

Enable signal (W) must be held high during the

WRITE instruction. Data input D is sampled on the

Low to High transition of the clock. After the last

data bit has been sampled, Chip Select (S) must

be brought Low before the next rising edge of the

clock (C), in order to start the self-timed program-

ming cycle, providing that the address is NOT in the

protected area. If the ST93CS46/47 is still per-

forming the programming cycle, the Busy signal (Q

= 0) will be returned if the Chip Select input (S) is

driven high, and the ST93CS46/47 will ignore any

data on the bus. When the write cycle is completed,

the Ready signal (Q = 1) will indicate (if S is driven

high) that the ST93CS46/47 is ready to receive a

new instruction.

Page Write

A Page Write instruction (PAWRITE) contains the

first address to be written followed by up to 4 data

words. The Write Enable signal (W) must be held

High duringthe Write instruction. Input address and

data are read on the Low to High transition of the

clock. After the receipt of each data word, bits

A1-A0 of the internal address register are incre-

mented, the high order bits A5-A2 remaining un-

changed. Users must take care by software to

ensure that the last word address has the same

four upper order address bits as the initial address

transmitted to avoid address roll-over.

After the LSB of the last data word, Chip Select (S)

must be brought Low before the next rising edge of

the Clock (C). The falling edge of Chip Select (S)

initiates the internal, self-timed write cycle. The

Page Write operation will not be performed if any

of the 4 words is addressing the protected area. If

the ST93CS46/47 is still performing the program-

ming cycle, the Busy signal (Q = 0) will be returned

if the Chip Select input (S) is driven high, and the

ST93CS46/47 will ignore any data on the bus.

When the write cycle is completed, the Ready

signal (Q = 1) will indicate (if S is driven high) that

the ST93CS46/47 is ready to receive a new instruc-

tion.

Write All

The Write All instruction (WRALL) is valid only after

the Protect Register has been cleared by executing

a PRCLEAR (Protect Register Clear) instruction.

The Write All instruction simultaneously writes the

whole memory with the same data word included

in the instruction. The Write Enable signal (W) must

be held High before and during the Write instruc-

tion. Input address and data are read on the Low

to High transition of the clock. If the ST93CS46/47

is still performing the programming cycle, the Busy

signal (Q = 0) will be returned if the Chip Select

input (S) is driven high, and the ST93CS46/47 will

ignore any data on the bus. When the write cycle

is completed, the Ready signal (Q = 1) will indicate

(if S is driven high) that the ST93CS46/47 is ready

to receive a new instruction.

MEMORY WRITE PROTECTION AND PROTECT

REGISTER

The ST93CS46/47 offers a Protect Register con-

taining the bottom address of the memory area

which has to be protected against write instruc-

tions. In addition to this Protect Register, two flag

bits are used to indicate the Protect Register status:

the Protect Flag enabling/disabling the protection

of theProtect Register and the OTP bit which, when

set, disables access to the Protect Register and

thus prevents any further modifications of this Pro-

tect Register value. The content of the Protect

struction, it may be read when using the PRREAD

instruction. A specific instruction PREN (Protect

protect instructions PRCLEAR, PRWRITE and

PRDS; this PREN instruction being used together

with the signals applied on the input pins PRE

(Protect Register Enable pin) and W (Write En-

able).

7/16

ST93CS46, ST93CS47

Accessing the Protect Register is done by execut-

ing the following sequence:

– WEN: execute the Write Enable instruction,

– PREN: execute the PREN instruction,

– PRWRITE, PRCLEAR or PRDS: the protection

then may be defined, in terms of size of the

protected area (PRWRITE, PRCLEAR) and

may be set permanently (PRDS instruction).

Protect Register Read

The Protect Register Read instruction (PRREAD)

outputs on the Data Output Q the content of the

Protect Register, followed by the Protect Flag bit.

The Protect Register Enable pin (PRE) must be

driven High before and during the instruction. As in

the Read instruction a dummy ’0’ bit is output first.

Since it is not possible to distinguish if the Protect

1’s, user must check the Protect Flag status (and

not the Protect Register content) to ascertain the

setting of the memory protection.

Protect Register Enable

The Protect Register Enable instruction (PREN) is

used to authorize the use of further PRCLEAR,

PRWRITE and PRDS instructions. The PREN

insruction does not modify the Protect Flag bit

value.

Note: A Write Enable (WEN) instruction must be

executed before the Protect Enable instruction.

Both the Protect Enable (PRE) and Write Enable

(W) input pins must be held High during the instruc-

tion execution.

Protect Register Clear

The Protect Register Clear instruction (PRCLEAR)

clears the address stored in the Protect Register to

all 1’s, and thus enables the execution of WRITE

and WRALL instructions. The Protect Register

Clear execution clears the Protect Flag to ’1’. Both

the Protect Enable (PRE) and Write Enable (W)

input pins must be driven High during the instruc-

tion execution.

Note: A PREN instruction must immediately pre-

cede the PRCLEAR instruction.

Protect Register Write

The Protect Register Write instruction (PRWRITE)

is used to write into the Protect Register the ad-

dress of the first word to be protected. After the

PRWRITE instruction execution, all memory loca-

tions equal to and above the specified address, are

protected from writing. The Protect Flag bit is set to

’0’, it can be read with Protect Register Read

instruction. Both the Protect Enable (PRE) and

Write Enable (W) input pins must be driven High

during the instruction execution.

Note: A PREN instruction must immediately pre-

cede the PRWRITE instruction, but it is not neces-

sary to execute first a PRCLEAR.

Protect Register Disable

The Protect Register Disable instruction sets the

One Time Programmable bit (OTP bit). The Protect

ONLY instruction which latches the Protect Regis-

ter content, this content is therefore unalterable in

the future. Both the Protect Enable (PRE) and Write

Enable (W) input pins must be driven High during

the instruction execution. The OTP bit cannot be

directly read, it can be checked by reading the

content of the Protect Register (PRREAD instruc-

tion), then by writing this same value into the Pro-

tect Register (PRWRITE instruction): when the

OTP bit is set, the Ready/Busy status cannot ap-

pear on the Data output (Q); when the OTP bit is

not set, the Busy status appear on the Data output

(Q).

A PREN instruction must immediately precede the

PRDS instruction.

READY/BUSY Status

When the ST93CS46/47 is performing the write

cycle, the Busy signal (Q = 0) is returned if S is

driven high, and the ST93CS46/47 will ignore any

data on the bus. When the write cycle is completed,

the Ready signal (Q = 1) will indicate, if S is driven

high, that the ST93CS46/47 is ready to receive a

new instruction. Once the ST93CS46/47 is Ready,

the Data Output Q is set to ’1’ until a new Start bit

is decoded or the Chip Select is brought Low.

COMMON I/O OPERATION

The Data Output (Q) and Data Input (D) signals can

be connected together, through a current limiting

resistor, to form a common, one wire data bus.

Some precautions must be taken when operating

the memory with this connection, mostly to prevent

a short circuit between the last entered address bit

(A0) and the first data bit output by Q. The reader

should refer to the SGS-THOMSON application

note ”MICROWIRE EEPROM Common I/O Opera-

tion”.

MEMORY WRITE PROTECTION (cont’d)

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ST93CS46, ST93CS47