256 X 256 DIFGITAL SWITCHING MATRIX

M3488

November 1994

256 x 256 DIGITAL SWITCHING MATRIX

PREL IMINARY DATA

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

256 INPUT AND 256 OUTPUT CHANNEL

CMOS DIGITAL SWITCHING MATRIX COM-

PATIBLE WITH M088

BUILDING BLOCK DESIGNED FOR LARGE

CAPACITY ELECTRONIC EXCHANGES, SUB-

SYSTEMS AND PABX

NO EXTRA PIN NEEDED FOR NOT-BLOCK-

ING SINGLE STAGE AND HIGHER CAPACITY

SYNTHESIS BLOCKS (512 or 1024 channels)

EUROPEAN TELEPHONE STANDARD COM-

PATIBLE (32 serial channels per frame)

PCM INPUTS AND OUTPUTS MUTUALLY

COMPATIBLE

ACTUAL INPUT-OUTPUT CHANNEL CON-

NECTIONS STORED AND MODIFIED VIA AN

ON CHIP 8-BIT PARALLEL MICROPROCES-

SOR INTERFACE

TYPICAL BIT RATE : 2Mbit/s

TYPICAL SYNCHRONIZATION RATE : 8KHz

(time frame is 125

5V P0WER SUPPLY

CMOS & TTL INPUT/OUTPUT LEVELS COM-

PATIBLE

HIGH DENSITY ADVANCED 1.2

m HCMOS3

PROCESS

Main instructions controlled by the microproc-

essor interface

CHANNEL CONNECTION/DISCONNECTION

OUTPUT CHANNEL DISCONNECTION

INSERTION OF A BYTE ON A PCM OUTPUT

CHANNEL/DISCONNECTION

TRANSFER TO THE MICROPROCESSOR OF

A SINGLE PCM OUTPUT CHANNEL SAMPLE

TRANSFER TO THE MICROPROCESSOR OF

A SINGLE OUTPUT CHANNEL CONTROL

WORD

TRANSFER TO THE MICROPROCESSOR OF

A SELECTED 0 CHANNEL PCM INPUT DATA

DIP40

PQFP44

ORDERING NUMBERS:

M3488B1

M3488Q1

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Test Conditions

Unit

Supply Voltage

-0.3 to 7

Input Voltage

-0.3 to V

+0.3

Off State Output Voltage

-0.3 to V

+0.3

Current at Digital Outputs

tot

Total Package Power Dissipation

1.5

stg

Storage Temperature Range

-65 to 150

Operating Temperature Range

0 to 70

Stresses above those l isted under ” Absolute Maximum Ratings” may cause permanent damage to the devi ce. This is a stress

rati ngs onl y and functional operation of the device at these or any other conditions above those indicated in the operating con-

di tions of this specificati on is not implied. Exposure to absolute maximum rating condi tio ns for extended periods may affect devi ce

rel ia bili ty.

1/18

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Value

Unit

Supply Voltage

4.75 to 5.25

Input Voltage

0 to 5.25

Off State Input Voltage

0 to 5.25

CLOCK

Freq.

Input Clock Frequency

4.096

MHz

SYNC Freq. Input Synchronization Frequency

KHz

Operating Temperature

0 to 70

CAPACITANCES (measurement freq. = 1MHz; T

= 0 to 70

C; unused pins tied to V

)

Symbol

Parameter

Pins (*)

Min.

Typ.

Max.

Unit

Input Capacitance

6 to 15; 26 to 30; 32 to 36

I/O

I/O Capacitance

20 to 24

Output Capacitance

1 to 4; 17 to 19; 25; 37 to 40

D.C. ELECTRICAL CHARACTERISTICS (T

amb

= 0 to 70

C, V

= 5V

5%)

All D.C. characteristics are valid 250

s after V

and clock have been applied.

Symbol

Parameter

Pins (*)

Test Condition

Min.

Typ.

Max.

Unit

ILC

Clock Input Low Level

-0.3

0.8

IHC

Clock Input High Level

2.4

Input Low Level

7 to 15

20 to 24

26 to 30

32 to 36

-0.3

0.8

Input High Level

7 to 15

20 to 24

26 to 30

32 to 36

Output High Voltage (Level)

17 to 25

= 5mA

2.4

Output High Current

= 2.4V

Output Low Voltage (Level)

1 to 4

37 to 40

17 to 25

= 5mA

0.4

Output Low Current

= 0.4V

Input Leakage Current

6 to 15

26 to 30

32 to 36

= 0 to V

Data Bus Leakage Current

17 to 24

= 0 to V

applied; Pins 35

and 36 tied to V

after Device Initialization

Supply Current

Clock Freq. = 4.096MHz

(*) T he pi n number i s referred to the DIP 40 ver sion.

M3488

5/18

A.C. ELECTRICAL CHARACTERISTICS (T

amb

= 0 to 70

C, V

= 5V

5%)

All A.C. characteristics are valid 250

s after V

and clock have been applied. C

is the max. capacitive load.

Sign al

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

CK (clock)

Clock Period

Clock Low Level Width

Clock High Level Width

Rise Time

Fall Time

230

100

244

SYNC

(frame pulse)

Low Level Setup Time

Low Level Hold Time

High Level Setup Time

High Level Width

PCM Input

Busses

Setup Time

Hold Time

+40

PCM Output

Busses

Open Drain

PD min

PD max

Propagation time

referred to CK low level

Propagation time

referred to CK high level

= 150pF

= 1K

110

140

RESET

Low Level Setup Time

Low Level Hold Time

High Level Setup Time

High level Width

WR, RD

REP

Low Lvel Width

High Level Width

Repetition Interval

between Active Pulses

High Level Setup Time

to Active Read Strobe

High Level Hold Time

from Active Write Strobe

Rise Time

Fall Time

REP

40 + 2 t

+ t

WL(CK)

+ t

R(CK)

100

see

formula

M3488

6/18

A.C. ELECTRICAL CHARACTERISTICS (continued)

Signal

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

CS1, CS2

SL(CS-WR)

HL(CS-WR)

SH(CS-WR)

HH(CS-WR)

SL(CS-RD)

HL(CS-RD)

SH(CS-RD)

HH(CS-RD)

Low level setup time

to WR falling edge

Low Level hold time

from WR rising edge

High Level setup time

to WR falling edge

High level hold time

from WR rising edge

Low level setup time

to RD falling edge

Low level hold time

from RD rising edge

High level setup time

RD falling edge

High level hold time

from RD

Active Case

Inactive Case

Active Case

Inactive Case

C/D

S(C/D-WR)

H(C/D-WR)

S(C/D)-RD)

H(C/D-RD)

Setup time to write

strobe end

Hold time from

write strobe end

Setup time to read

strobe start

Hold time from read

strobe end

130

A1, S1,

A2, S2

(match

inputs)

S(match-WR)

H(match-WR)

S(match-RD)

H(match-RD)

Setup time to write

strobe end

Hold time from

strobe end

Setup time to read

strobe start

Hold time from read

strobe end

130

(data

ready)

Low state width

DR output delay

from write strobe end

(active command)

Instructions 5 and 6

Instruction 5, C

150pF

4.t

2.t

7.t

D0 to D7

(interface

bus)

S(BUS-WR)

H(BUS-WR)

PD(BUS)

HZ(BUS)

Input setup time to

write strobe end

Input hold time

from write strobe end

Propagation time

from (active) falling

Edge of read strobe

Propagation time

from (active) rising

Edge of read strobe

to high impedance state

= 200pF

130

120

A.C. TESTING, OUTPUT WAVEFORM

A.C. testing inputs are driven at 2.4V for a logic ”1” and 0.45V for a logic ”0”, timing measurement are made at

2.0V for a logic ”1”and 0.8V for a logic ”0”.

M3488

7/18

READ OPERATION TIMING

GENERAL DESCRIPTION

The M3488 is intendedfor large telephoneswitching

systems, mainly central exchanges, digital line con-

centrators and private branch exchanges where a

distributed microcomputer control approach is ex-

tensively used. It consists of a speech memory

(SM), a control memory (CM), a serial/parallel and

a parallel/serial converter, an internal parallel bus,

an interface (8 data lines, 11 control signals) and

dedicated control logic.

By means of repeated clock division two timebases

are generated. These are preset from an external

synchronization signal to two specific count num-

bers so that sequential scanning of the bases give

synchronous addresses to the memories and I/O

channel controls. Different preset count numbers

are needed because of processing delays and

data path direction. The timebase for the input chan-

nels is delayed and the timebase for output chan-

nels is advanced with respect to the actual time.

Each serial PCM input channel is converted to par-

allel data and stored in the speech memory at the

beginning of any new time slot (according to first

timebase) in the location determined by input pin

number and time slot number. The control memory

CM maintains the correspondencesbetween input

and output channels. More exactly, for any output

pin/outputchannel combination the control memory

gives either the full address of the speech memory

location involved in the PCM transfer or an 8-bit

word to be supplied to the parallel/serial output con-

verter. A 9

bit at each CM location defines the data

source for output links, low for SM, high for CM.

The late timebase is used to scan the output chan-

nels and to determine the pins to be serviced within

each channel ; enough idle cycles are left to the mi-

croprocessor for asynchronousinstruction process-

ing.

Two 8-bit registers OR1 and OR2 supply feedback

data for control or diagnosticpurposes ; OR1 comes

from internal bus i.e. from memories, OR2 gives an

opcode copy and additional data to the microcom-

puter. A four byte-five bit stack register and an in-

struction register, under microcomputer control,

store input data available at the interface.

Dedicated logic, under control of the microprocessor

interface, extracts the 0 channel content of any se-

lected PCM input bus, using spare cycles of SM.

M3488

9/18

PIN DESCRIPTION

D7 to D0

Data bus pins. The bidirectional bus is usedto trans-

fer data and instructions to/fromthe microprocessor.

D0 is the least significant digit. The output bus is 8

bits wide ; input is only 5 bits wide. (D4 to D0)

The bus is tristate and cannot be used while RESET

is held low.

The meaning of input data, such as bus or channel

numbers, and of expected output data is specified

in detail by the instruction description. (Pagg. 12-14)

C/D (pin 30)

Input control pin, select pin. In a write operation

C/D = 0 qualifies any bus content as data, while

C/D = 1 qualifies it as an opcode. In a read operation

OR1 is selected by C/D = 0, OR2 by C/D = 1.

A1, S1, A2, S2

Address select or match pins. In a multi-chip con-

figuration (e.g. a single stage matrix expansion), us-

ing the same CS pins, the match condition (A1 = S1

and A2 = S2) leaves the commandinstruction as de-

fined; on the contrary the mismatch condition modi-

fies the execution as follows : instructions 1 and 3

are reversed to channel disconnection, instruction 5

is unaffected, instructions 2-4-6 are cancelled (not

executed).

Bus reading takes place only on match condition,

instruction flow is in any case affected.

Eachpins couple is commutative : in a multichip con-

figuration pins S1 and S2 give a hard-wired address

selection for individual matrixes, while in single con-

figuration S1 and A1 or S2 and A2 are normally

tied together.

CS1, CS2

Commutative chip select pins. They enable the de-

vice to perform valid read/write operations (active

low). Two pins allow row/column selection with dif-

ferent types of microprocessors ; normally one is

tied to ground.

Pin WR, when CS1 and CS2 are low, enables data

transfer from microprocessor to the device. Data or

opcode and controls are latched on WR rising edge.

Becauseof internal clock resynchronizationone sin-

gle additional requirement is recommended in order

to produce a simultaneous instruction execution in

a multichip configuration : WR rising edge has to be

20 to 20 + t

WL(CK)

nsec late relative to clock falling

edge.

When CS1 and CS2 are low and match condition ex-

ists, a low level on RD enables a register OR1 or

OR2 read operation, through the bidirectional bus.

In addition, the rising edge of RD latches C/D and

the match condition pins in order to direct the inter-

nal flow of operations. Because of internal clock

resynchronization, one single additional require-

ment is recommended in order to produce a simul-

taneous instruction flow in a multichip configuration:

the RD rising edge has to be 20 to 20 + t

WL(CK)

nsec

late relative to clock falling edge.

Data ready. Normally high, DR output pin goes low

to tell the microprocessor that :

a) the instruction code was found to be invalid ;

b) executing instruction 5 an active output channel

was found in the whole matrix array, that is a CM

word not all ”ones” was found in a configuration of

devices sharing the same CS pins ;

c) executing instruction 6 ”0 channel extraction” took

place and OR2 was loaded with total number of

messages inserted on 0 time slot.

DR is active low about two clock cycles in case b

and c ; in case a it is left low until a valid instruction

code is supplied.

RESET

RESET control pin is normally used at the very be-

ginning to initialize the device or the network. Any

logical status is reset and CM is set to all ”ones” after

RESET going low.

The internal initialization routine takes one time

frame whatever the RESET width on low level (mini-

mum one cycle roughly), but it is repeatedan integer

number of time frames as long as RESET is found

low during 0 time slot.

Initialization pulls the interface bus immediately to a

high impedance state. After the CM has been set to

all ”ones” the PCM output channels are also set to

high impedance state.

CLOCK

Input master clock. Typical frequency is 4.096MHz.

First division gives an internal clock controlling the

input and output channels bit rate.

SYNC

Input synchronization signal is active low. Typical

frequency is 8kHz.

M3488

11/18

Internal time bases are forced by synchronism to an

assigned count number in order to restore channels

and bit sequential addressing to a known state.

Count difference between the bases is 32, corre-

spondingto two time slots, that is the minimum PCM

propagation time, or latency time.

INP PCM 7 to INP PCM 0

PCM input busses or pins ; they accept a standard

2Mbit/s rate. Bit 1 (sign bit) is the first of the serial

sequence ; in a parallel conversion it is left adjusted

as the most significant digit.

OUT PCM 7 to OUT PCM 0

PCM output busses or pins ; bit rate and organiza-

tion are the same as input pins.

Output buffers are open drain CMOS .

The device drives the output channels theoretically

one bit time before they can be exploited as logical

input channels (bit and slot compatibility is pre-

served): this feature allows inputs and outputs to be

tied together cancelling any analog delay of digital

outputs up to

DEL max

= t

bit

- t

PD(PCM)max

+ t

PD(PCM)min

MIXED RD and WR OPERATIONS

In principle RD and WR operations are allowed in

any order within specification constraints.

In practive, only one control pin is low at any given

time when CS1 and CS2 are enabled.

If by mistake or hardware failure both RD and WR

pins are low, the interface bus is internally pushed

to tristate condition as long as WR is held low and

input registers are protected.

Registers OR1 and OR2 can be read in any order

with a single RD strobe using C/D as multiplexing

control ; never the less this procedure is not recom-

mended because the device is directed for instruc-

tion flow only according to data latched by RD rising

edge.

Multiple RD operationsof the same kind are allowed

without affecting the instruction flow : only ”new”

OR1 or OR2 read operations step the flow.

Input and output registers are held for sure in the

previous state for the first 3 cycles following an op-

code or an OR2 read.

FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS

The device, under microprocessor control, performs

the following instructions :

1 CHANNEL CONNECTION

2 CHANNEL DISCONNECTION

3 LOADING OF A BYTE ON A PCM OUTPUT

CHANNEL

4 TRANSFER OF A SINGLE PCM OUTPUT

CHANNEL SAMPLE

5 TRANSFER OF A SINGLE OUTPUT

CHANNEL CONTROL WORD

6 TRANSFER OF A SELECTED 0 CHANNEL PCM

INPUT DATA ACCORDING TO AN 8-BIT MASK

PREVIOUSLY STORED IN THE ”EXPECTED

MESSAGES” REGISTER

The instruction flow is as follows.

Any input protocol is started by the microprocessor

interface loading the internal stack register with 2

bytes (4 bytes for instructions 1 and 3) qualified as

data bytes by C/D = 0 and a specific opcode quali-

fied by C/D = 1 (match condition is normally

needed).

After the code is loaded in the instruction register it

is immediately checked to see whether it is ac-

ceptable and if not it is rejected. If accepted the

instruction is also processed as regards match con-

dition and is appended for execution during the

memories’ spare cycles.

Four cases are possible :

a) the code is not valid ; executioncannot take place,

the DR output pin is reset to indicate the error ; all

registers are saved ;

b) the code is valid for types 2, 4 and 6 but it is un-

matched ; execution cannot take place, DR is not af-

fected.

c) the code is valid for types 1 and 3 and it is un-

matched ; the instruction is interpreted as a channel

disconnection.

d) the code is valid and is either matched or of type

5 ; the instruction is processed as received.

Validation control takes only two cycles out of a total

execution time of 4 to 7 cycles ; the last operation is

updating of the content of registers OR1 and OR2,

according to the following instruction tables.

M3488

12/18

During a very long internal operation (device initiali-

zation after RESET going high or execution of in-

struction 6) a new set of data bytes with a valid op-

code is accepted while a wrong code is rejected. At

the end of the current routine execution takes place

in the same way as described before.

At the end of an instruction it is normally recom-

mended to read one or both registers. To exploit in-

struction 6, however, it is mandatory to read register

OR2. This is because instruction 6, used between

other short instructions of type 1 to 5, must have pri-

ority and can be enabled only after the short instruc-

tions have been completed. Instruction 6 normally

has a long process and a special flow which is de-

scribed below.

First a not-all-zero mask is stored in the ”expected

messages” register and in another ”background”

instruction 6 which is called ”channel 0 extraction”

and is repeated at the beginning of any new time

frame.At the beginningof the time frame a new copy

of activated channels to be extracted is made from

the ”background register” and put in the ”expected

messages” register. In addition the latter register is

modified to indicate the exact number of messages

that have arrived. The term messages covers any

input 0 channeldata with starting sequencedifferent

from the label 01. So using this label the number of

expected messages can be reduced to correspond

to the number of effective messages. If and only if

the residual number is different from zero will the de-

vice start the extraction protocol at the end of the