SINGLE CHIP 4 MBIT FLASH AND 256 KBIT PARALLEL EEPROM MEMORY

1/28

November 1999

M39432

Single Chip 4 Mbit Flash Memory and

256 Kbit Parallel EEPROM

Multiple Memories on a Single Chip:

– 4 Mbit Flash Memory (organised as 8 sectors)

– 256 Kbit EEPROM

– 64 Byte One Time Programmable Memory

CONCURRENT Mode (Read Flash while

writing to EEPROM)

WRITE, PROGRAM and ERASE Status Bits

2.7V to 3.6V Single Supply Voltage for

PROGRAM, ERASE and READ Operations

100 ns Access Time (Flash and EEPROM

blocks)

Low Power Consumption

– 60

A Stand-by mode (maximum)

– Deep Power Down mode:

A (maximum), 200 nA (typical)

Standard Flash Memory Package

100,000 Erase/Write Cycles (minimum)

10 Year Data Retention (minimum)

DESCRIPTION

The M39432 is a single supply voltage memory

device combining Flash memory and EEPROM on

a single chip. The memory is mapped in two

Figure 1. Logic Diagram

AI01946

A0-A18

DQ0-DQ7

VCC

M39432

VSS

R/B

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

EEPROM Block Enable

Flash Block Enable

Output Enable

Write Enable

R/B

Ready/Busy Output

Supply Voltage

Ground

TSOP40 (NC)

10 x 20 mm

M39432

2/28

blocks: 4 Mbit of Flash memory and 256 Kbit of

EEPROM. Each block operates independently

during a Write cycle: in concurrent mode, the

Flash Memory can be read while the EEPROM is

being written.

There is also a 64 byte row of OTP (one time

programmable) EPROM.

The M39432 EEPROM block may be written

bytewise or by a page at a time (up to 64 bytes).

The integrity of the data can be secured with the

help of the Software Data Protection (SDP).

The M39432 Flash Memory block offers 8 sectors,

each one 64 KByte in size. Each sector may be

erased individually, and programmed a byte at a

time. Each sector can be separately protected and

unprotected against Program and Erase. Sector

erasure may be suspended, while data is read

from other sectors of the Flash memory block (or

from the EEPROM block), and then resumed. The

Flash memory block is functionally compatible with

the M29W040 (4 Mbit Single Voltage Flash

Memory).

During a Program or Erase cycle in the Flash

memory or during a Write cycle in the EEPROM,

the status of the M39432 internal logic can be read

on the Data Output pins DQ7, DQ6, DQ5 and

DQ3.

SIGNAL DESCRIPTION

Address Inputs (A0-A18)

The address inputs for the memory array are

latched during a write operation. The EEPROM

block is selected by the EE input, and the Flash

memory block the EF input. A0-A14 access

locations in the EEPROM block; A0-A18 access

locations in the Flash memory block.

When V

(as specified in Table 11) is applied on

the A9 address input, additional device-specific

information can be accessed:

– Read the Manufacturer identifier

– Read the Flash block identifier

– Read/Write the EEPROM block identifier

– Verify the Flash Sector Protection Status.

Figure 2. TSOP Connections

Note: 1. NC = Not Connected.

DQ0

R/B

A13

A11

DQ7

A14

VSS

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A17

A16

A12

A18

VCC

A15

AI01947

M39432

A10

Table 2. Absolute Maximum Ratings

Note: 1. Stresses above those listed may cause permanent damage to the device. These are stress ratings only and operation of the device

at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to

Absolute Maximum Rating conditions for extended periods may affect device reliability. Please see the STMicroelectronics SURE

Program and other relevant quality documents.

2. Minimum voltage may undershoot to –2 V, during transition and for less than 20 ns.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

–40 to 85

°C

BIAS

Temperature Under Bias

–50 to 125

°C

STG

Storage Temperature

–65 to 150

°C

1,2

Input or Output Voltage (except A9)

–0.6 to 7

Supply Voltage

–0.6 to 7

, V

1,2

A9, G and EF Voltage

–0.6 to 13.5

3/28

M39432

Data Input/Output (DQ0-DQ7)

During a Write operation, one data byte is latched

into the device when Write Enable (W) and one

Chip Enable (EF or EE) are driven low.

During a Read operation, the output presented on

these pins is valid when Output Enable (G) and

one Chip Enable (EF or EE) are driven low. The

output is high impedance when the chip is

deselected (both EE and EF driven high) or the

outputs are disabled (G driven high).

Read operations are used to output:

– bytes in the Flash memory block

– bytes in the EEPROM block

– the Manufacturer Identifier

– the Flash Sector Protection Status

– the Flash Block Identifier

– the EEPROM Identifier

– the OTP row.

Chip Enable (EE and EF)

Each Chip Enable (EE or EF) causes the memory

control logic, input buffers, decoders and sense

amplifiers to be activated. When the EE input is

driven high, the EEPROM memory block is not

selected; when the EF input is driven high, the

Flash memory block is not selected. Attempts to

access both EEPROM and Flash blocks (EE low

and EF low) are forbidden. Switching between the

two chip enables (EE and EF) must not be made

on the same clock cycle, a delay of greater than

EHFL

must occur.

The M39432 is in stand-by mode when both EF

and EE are high (when no internal Erase or

programming cycle is running). The power

consumption is reduced to the stand-by level and

the outputs are held in the high state, independent

of the Output Enable (G) or Write Enable (W)

inputs.

After 150 ns of inactivity, and when the addresses

are driven at CMOS levels, the chip automatically

enters a pseudo-stand-by mode. Power

consumption is reduced to the CMOS stand-by

level, while the outputs continue to drive the bus.

Output Enable (G)

The Output Enable gates the outputs through the

data buffers during a Read operation. The data

outputs are left floating in their high impedance

state when the Output Enable (G) is high.

During Sector Protect (Figure 8) and Sector

Unprotect (Figure 9) operations (for the Flash

memory block only), the G input must be held at

(as specified in Table 11).

Write Enable (W)

Addresses are latched on the falling edge of W,

and Data Inputs are latched on the rising edge of

Ready/Busy (R/B)

When the EEPROM block is engaged in an

internal Write cycle, the Ready/Busy output shows

the status of the device:

– R/B is 0 when a Write cycle is in progress

– R/B is Hi-Z when no Write cycle is in progress

The Ready/Busy pin does not show the status of a

Program or Erase cycle in the Flash memory.

This pin can be used to show the status of the

EEPROM block, even when reading data (or

fetching instructions) from the Flash memory

block.

Figure 3. Flash Block Sectors

64K Bytes Block

AI01362B

7FFFFh

6FFFFh

5FFFFh

4FFFFh

3FFFFh

2FFFFh

1FFFFh

0FFFFh

TOP

ADDRESS

70000h

60000h

50000h

40000h

30000h

20000h

10000h

00000h

BOTTOM

ADDRESS

A18

64K Bytes Block

A17

A16

M39432

4/28

This open drain output can be wire-ORed, using

an external pull-up resistor, when several M39xxx

devices are used together.

Supply Voltage

The V

Supply Voltage supplies the power for

the device. The M39432 cannot be written when

the V

Supply Voltage is less than the Lockout

Voltage, V

LKO

. This prevents Bus Write operations

from accidentally damaging the data during power

up, power down and during power surges.

A 100 nF capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin, to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations.

Ground

The V

Ground is the reference for all voltage

measurements.

DEVICE OPERATION

The M39432 memory device is addressed via 19

inputs (A0-A18) and carries data on 8 Data Inputs/

Outputs (DQ0-DQ7). There are four other control

inputs: Chip Enable EEPROM (EE), Chip Enable

Flash Memory (EF), Output Enable (E) and Write

Enable (W).

The Chip Enable inputs (EF or EE) are used

mainly for power control (turning the chip on and

off) and for block selection (selecting the

EEPROM block or the Flash memory block). The

gating of data to the DQ0-DQ7 pins should be

controlled using the Output Enable input (G).

The permitted operating modes of the device are

listed in Table 3.

Read

For a Read operation, the Output Enable (G) and

one Chip Enable (EF or EE) must be driven low.

As noted on the previous page, Read operations

are used to read the contents of:

– bytes in the Flash memory block

– bytes in the EEPROM block

– the Manufacturer Identifier

– the Flash Sector Protection Status

– the Flash Block Identifier

– the EEPROM Identifier

– the OTP row.

The instruction sequences for selecting between

these areas is summarized in Table 4.

Write

Writing data requires:

– a Chip Enable (either EE or EF) to be low

– the Write Enable (W) to be low and the Output

Enable (G) to be high.

Addresses in the Flash memory block (or the

EEPROM block) are latched on the falling edge of

W or EF (or EE) whichever occurs the later. The

data to be written to the Flash memory block (or

EEPROM block) is latched on the rising edge of W

or EF (or EE) whichever occurs first.

The Write operation is used in two contexts:

– to write data to the EEPROM memory block

– to enter the sequence of bytes that makes up

one of the instructions shown in Table 4.

The programming of a byte of Flash memory

involves one of these instructions (as described in

the section entitled “Instructions” on this page).

Specific Read and Write Operations

Device specific information includes the following:

– Read the Manufacturer Identifier

– Read the Device Identifier

– Define the Flash Sector Protection

– Read the EEPROM Identifier

– Write the EEPROM Identifier

Table 3. Operations

Note: 1. X = V

or V

Operation

DQ0 - DQ7

Read

Read from Flash Block

Read from EEPROM Block

Write

Write to Flash Block

Write to EEPROM Block

Output Disable

Hi-Z

Stand-by

Hi-Z

5/28

M39432

Table 4. Instructions

Note: 1. AAh @ 5555h means “Write the value AAh at the address 5555h”.

2. This instruction can also be performed as a Verify operation with A9=V

(please see the section entitled “Flash Sector Protection

and Unprotection” on page 18).

3. Addresses of additional sectors to be erased must be entered within a time-out of 80

s of each other.

Instruction

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Read

Manufacturer

Identifier

AAh

@5555h

55h

@2AAAh

90h

@5555h

Read Identifier

with (A0,A1,A6)

set to (0,0,0)

Read Flash

Identifier

AAh

@5555h

55h

@2AAAh

90h

@5555h

Read Identifier

with (A0,A1,A6)

set to (1,0,0)

Read OTP Row

AAh

@5555h

55h

@2AAAh

90h

@5555h

Read

Byte 1

Read

Byte 2

Read

Byte N

Read Sector

Protection Status

AAh

@5555h

55h

@2AAAh

90h

@5555h

Read Identifier

with (A0,A1,A6)

set to (0,1,0)

Program a Byte of

Flash Memory

AAh

@5555h

55h

@2AAAh

A0h

@5555h

Data

@ Address

Erase a Sector of

Flash Memory

AAh

@5555h

55h

@2AAAh

80h

@5555h

AAh

@5555h

55h

@2AAAh

30h

@ Sector

address

30h

@ Sector

address

Erase the Whole

of Flash Memory

AAh

@5555h

55h

@2AAAh

80h

@5555h

AAh

@5555h

55h

@2AAAh

10h

@5555h

Suspend Sector

Erase

B0h

@any

address

Resume Sector

Erase

30h

@any

address

EEPROM Power

Down

AAh

@5555h

55h

@2AAAh

30h

@5555h

Deep Power

Down

20h

@5555h

SDP Enable

(EEPROM)

AAh

@5555h

55h

@2AAAh

A0h

@5555h

Write

Byte 1

Write

Byte 2

Write

Byte N

SDP Disable

(EEPROM)

AAh

@5555h

55h

@2AAAh

80h

@5555h

AAh

@5555h

55h

@2AAAh

20h

@5555h

Write OTP Row

AAh

@5555h

55h

@2AAAh

B0h

@5555h

Write

Byte 1

Write

Byte 2

Write

Byte N

Return (from OTP

Read or

EEPROM Power

Down)

F0h

@any

address

Reset

AAh

@5555h

55h

@2AAAh

F0h

@any

address

Reset (short

instruction)

F0h

@any

address

M39432

6/28

To access these, A9 is held at V

(as specified in

Table 11) and the specific logic levels, shown in

Table 5, are applied to the address inputs A0, A1

and A6.

The OTP row is accessed with a specific software

sequence, as described in the section entitled

“Writing the OTP Row” on page 11.

Instructions

Instructions consist of a sequence of specific Write

operations, as summarized in Table 4. The time

between two consecutive bytes must be shorter

than the time-out value (t

WLWL

Each received byte is decoded sequentially, and

not executed as a standard Write operation. The

overall instruction is executed when the correct

number of bytes have been properly received.

The sequence must be followed exactly. If an

invalid combination of instruction bytes occurs, or

time-out between two consecutive bytes, the

device logic resets itself to the Read state, when

addressing the Flash block, or is directly decoded

as a single operation, when addressing the

EEPROM block.

The M39432 instructions set, as summarized in

Table 4, includes:

Program a byte in the Flash memory block

Read the Protection Status of a Flash Sector

Erase instructions:

– Flash Sector Erase

– Flash Block Erase

– Flash Sector Erase Suspend

– Flash Sector Erase Resume

EEPROM Power Down

Deep Power Down

Change the EEPROM software write protection:

– Enable SDP

– Disable SDP

OTP row access:

– Write the whole OTP row (once)

– Read from the OTP row

Reset and Return

Read identifiers:

– Read the Manufacturer Identifier

– Read the Flash Block Identifier

For efficiency, each instruction consists of a two-

byte escape sequence, followed by a command

byte or a confirmation byte. The escape sequence

consists of writing the value AAh at address

5555h, in the first cycle, and the value 55h at

address 2AAAh, in the second cycle.

In the case of the Erase instructions, an additional

escape sequence is required, for final confirmation

that the instruction is the intended one.

POWER SUPPLY AND CURRENT

CONSUMPTION

Power Up

The M39432 internal logic is reset, to Read mode,

upon a power-up event. All Write operations to the

EEPROM are inhibited for the first 5 ms.

No new Write cycles can be started when V

below V

LKO

(as specified in Table 11). However,

for maximum security of the contents of the

memory, and to remove the possibility of a byte

being written on the first rising edge of EF, EE or

W, at least one of EF, EE or W should be tied to

during the power-up process.

Stand-by

When both EE and EF are high, the memory

enters Stand-by mode, and the Data Input/Output

pins are placed in the high-impedance state. To

reduce the Supply Current to the Stand-by Supply

Current, EE and EF should be held within

±0.2V.

If the Stand-by mode is set during a Program or

Erase cycle, the memory continues to use the

Supply Current until the cycle is complete.

Table 5. Device Identifier Operations

Note: 1. X = Don’t Care.

Instruction

Other Address

Lines

DQ0 - DQ7

Read Manufacturer

Identifier

Don’t Care

20h

Read Flash Block

Identifier

Don’t Care

0E3h

Read EEPROM

Block Identifier

Don’t Care

64 user-

defined bytes

7/28

M39432

Automatic Stand-by

If CMOS levels (V

±0.2V) are used to drive the

bus, and the bus is inactive for more than 150 ns,

the memory enters the Automatic Stand-by state.

The internal supply current is reduced to the

Stand-by Supply Current, I

CC3

Deep Power Down

The I

consumption mode can be reduced to a

minimum using the Deep Power Down instruction

(as shown in Table 4). The device is set in a sleep

mode until the next Reset instruction is executed.

EEPROM Power Down

The M39432 can power-down the EEPROM block

using the specific instruction shown in Table 4.

Once in this state, the EEPROM block is no longer

accessible, until a Return instruction is executed.

READ

Read operations and instructions can be used:

– to read the contents of the memory array (Flash

memory block or EEPROM block)

– to read the memory array status and identifiers

(Flash memory block or EEPROM block).

Read Data (from Flash Memory or EEPROM)

For a Read operation, the Output Enable (G) and

one Chip Enable (EF or EE) must be driven low.

Read the Manufacturer Identifier

There are two alternative methods for reading the

Manufacturer Identifier: using a Read operation or

using a Read instruction.

Read Operation.

The Manufacturer Identifier can

be read with a Read operation by applying V

(as

specified in Table 11) on A9, and the logic levels

specified in Table 5 applied to A0, A1, A6.

Read Instruction.

The Manufacturer Identifier can

also be read using an instruction composed of four

operations: three specific Write operations (as

specified in Table 4) and a Read operation. This

either accesses the Manufacturer Identifier, the

Flash Block Identifier or the Flash Sector

Protection Status, depending on the levels that are

being applied to A0, A1, A6, A16, A17 and A18.

Read the Flash Block Identifier

Similarly, there are two alternative methods for

reading the Flash Block Identifier (E3h): using a

Read operation or using a Read instruction.

Please see the previous section, entitled “Read

the Manufacturer Identifier”, and Table 5 and

Table 4 for details.

Read the EEPROM Block Identifier

The EEPROM Block Identifier (64 bytes, user de-

fined) can be read with a single Read operation by

holding A6 low and A9 at V

(see Table 5).

Read the OTP Row

The OTP row is mapped in the EEPROM block.

With EE held low, and EF held high, an EEPROM

Read instruction is composed, as specified in

Table 6. Status Bits

Note: 1. X = Not a guaranteed value, can be read either as ‘1’ or ‘0’.

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Flash

Data

Polling

Toggle

Flag

Error

Flag

Erase

Time-

Out

EEPROM

Data

Polling

Toggle

Flag

Figure 4. Data Polling Flowchart

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL

PASS

AI01369B

DQ7

DATA

YES

DQ5

= 1

DQ7

DATA

YES

M39432

8/28

Program cycles, and after the sixth pulse on the W

line for Erase cycles. The Data Polling Read

instruction must address the same location as the

byte that is being programmed, or within the same

Flash sector as the one that is being erased.

Toggle flag, DQ6. During an internal Write,

Program or Erase cycle, DQ6 toggles between ’0’

and ’1’, on successive Read accesses to any byte

of the memory (when either G, EE or EF is held

low).

When the internal cycle is complete, the toggling is

stopped, and the data read on DQ0-DQ7 is that of

the addressed memory byte. A subsequent

Reading at the same address will result in the

same data being read.

This alternative method for detecting when the

internal Write, Program or Erase cycle has

completed, is shown in the flowchart in Figure 5.

When an internal cycle is in progress, data bit DQ6

toggles between ‘1’ and ‘0’ for successive Read

operations. When DQ6 no longer toggles and the

Error bit DQ5 is ’0’, the operation is complete. To

determine if DQ6 has toggled, each poll requires

two consecutive Read operations to see if the data

read is the same each time.

For the flash memory block, data Toggling is

effective after the fourth pulse on the W line for

Table 4. This consists of the writing of three

specific data bytes at three specific memory

locations (each location on a different page) as a

prefix to reading the OTP row content.

When accessing the OTP row, only the least

significant bits of the address bus (A0 to A6) are

decoded (of which A6 must be low).

Each Read of the OTP row has to be followed by

the Return instruction (as shown in Table 4).

Read the Flash Sector Protection Status

There are two alternative methods for reading the

Flash Sector Protection Status: using a Verify

operation with A9=V

(as described on page 18)

or using a Read instruction as described in the

section entitled “Read the Manufacturer Identifier”,

starting on page 7.

Using the Read instruction, the logic levels on A0,

A1, A6 select the correct instruction, while A16,

A17 and A18 specify which sector is being

addressed. This returns the value 01h if the Flash

sector is protected, and the value 00h if the Flash

sector is not protected.

Read the Status Bits

The latency period of Write, Erase and Program

cycles can be monitored by the application

software, by using the M39432 status bits. The

Ready/Busy pin provides the status information

during a write cycle to the EEPROM block (though

not to the Flash memory block). An internal status

programming or erase cycle. A Read operation,

during the program or write cycle, causes the

contents of this register to be presented to the I/O

ports (DQ0-DQ7), as summarized in Table 6.

Data Polling flag, DQ7. The I/O lines (DQ0-

DQ7) are first used as inputs, carrying the data

that is to be written to the EEPROM or

programmed in the Flash memory. Once the Write

or Program cycle is underway, these lines become

outputs (and can be read using a normal Read

operation). The value presented on DQ7 is the

inverse of the data bit that was presented by the

user. When the cycle is complete, the lines remain

as outputs, and the value that is presented on DQ7

is the non-inverted value that was originally

specified for writing.

The suitable algorithm for using this method of

polling is shown in Figure 4. When a Write or

Program cycle is in progress, data bit DQ7 is set to

the complement of the original data bit 7 (or to ‘0’

in the case of an Erase cycle in the Flash memory

block). When DQ7 is identical to the old data (or to

‘1’ in the case of an Erase cycle in the Flash

memory block) and the Error bit (DQ5) is still ’0’,

the cycle is complete.<