8/16-BIT MICROCONTROLLER (MCU) WITH 16-48K ROM, OTP, EPROM, ON SCREEN DISPLAY AND VOLTAGE TUNING OUTPUT

ST9291

July 1995

16-48K ROM HCMOS MCU WITH

ON SCREEN DISPLAY AND VOLTAGE TUNING OUTPUT

(Ordering Information at the end of the Datasheet)

PSDIP42

PSDIP56

Device

ROM

RAM

PACKAGE

ST9291J2/N2

16K

384

PSDIP42/56

ST9291J3/N3

16K

640

PSDIP42/56

ST9291J4/N4

24K

384

PSDIP42/56

ST9291J5/N5

24K

640

PSDIP42/56

ST9291J6/N6

32K

640

PSDIP42/56

ST9291J7/N7

48K

640

PSDIP42/56

DEVICE SUMMARY

RUN, WFI and HALT modes

Minimum instruction cycle time: 500ns

(12MHz internal)

16 to 48K bytes of ROM,

384/640 bytes of RAM,

224 general purpose registers available as RAM,

accumulators or index registers (Register File)

42-lead Shrink DIP package or

56-lead Shrink DIP package

Interrupt handler and Serial Peripheral Interface

as standard features

31 (42 pin package) / 42 (56 pin package) fully

programmable I/O pins

34 character x15 rows software programmable

On Screen Display module with colour, italic, un-

derline, flash, transparent and fringe attribute

options

14-bit Voltage Synthesis for tuning reference

voltage.

8 8-bit PWM D/A outputs with repetition frequency

2 to 32kHz and 12V Open Drain Capability

16 bit Timer with 8 bit Prescaler, able to be used

as a Watchdog Timer

16-bit programmable Slice Timer with 8-bit pres-

caler

3 channel Analog to Digital Converter, with inte-

gral sample and hold, fast 5.75

s conversion

time, 6-bit guaranteed resolution

Rich Instruction Set and 14 Addressing modes

Division-by-Zero trap generation

Versatile Development tools, including assembler,

linker, C-compiler, archiver, graphic oriented de-

bugger and hardware emulators

Real Time Operating System

Windowed EPROM parts available for prototyp-

ing and pre-production development phases

FUNCTIONAL DESCRIPTION

1/20

VR01740B

Figure 1. 42 Pin Shrink DIP Pinout

Pin

name

P2.0/INT7

RESET

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

P3.7

P3.6

P3.5

P3.4

P3.3/B

P3.2/G

P3.1/R

P3.0/FB

P5.1/SDIO

P5.0/SCK/INT2

Pin

name

P2.1/INT5/AIN1

P2.2/INT0/AIN2

P2.3/INT6/VSO1

P2.4/NMI

P2.5/AIN3/VSO2

OSCIN

OSCOUT

P4.7/PWM7/

EXTRG (AD)

P4.6/PWM6

P4.5/PWM5

P4.4/PWM4

P4.3/PWM3

P4.2/PWM2

P4.1/PWM1

P4.0/PWM0

VSYNC

HSYNC

PLLR

PLLF

ST9291J Pin Description

Pin

name

P2.1/INT5/AIN1

P2.0/INT7

RESET

P0.7

P0.6

P0.5

N.C

.(1)

P0.4

P0.3

P0.2

P0.1

P0.0

N.C.

(1)

(2)

N.C.

(1)

P3.7

P3.6

P3.5

P3.4

P3.3/B

P3.2/G

P3.1/R

P3.0/FB

P5.3

P5.2

P5.1/SDIO

P5.0/SCK/INT2

(2)

Pin

name

P2.2/INT0/AIN2

P2.3/INT6/VSO1

P2.4/NMI

P2.5/AIN3/VSO2

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

OSCIN

OSCOUT

P4.7/PWM7/

EXTRG (AD)

P4.6/PWM6

P4.5/PWM5

P4.4/PWM4

P4.3/PWM3

P4.2/PWM2

P4.1/PWM1

P4.0/PWM0

VSYNC

HSYNC

PLLR

PLLF

ST9291N Pin Description

VR01740A

Figure 2. 56 Pin Shrink DIP Pinout

Notes (N Package only) :

1. N.C. means “not connected”

2. Pins 14 and 28 (VDD) are internally connected

ST9291

2/20

GENERAL DESCRIPTION

The ST9291 is a ROM member of the ST9 family of

microcontrollers, completely developed and pro-

duced by SGS-THOMSON Microelectronics using

a proprietary n-well HCMOS process.

The ROM parts are fully compatible with their

EPROM and OTP (One-Time Programmable) ver-

sions, which may be used for the prototyping and

pre-production phases of development.

The nucleus of the ST9291 is the advanced ST9

Core which includes the Central Processing Unit

(CPU), the Register File, a 16-bit Timer/Watchdog

with 8-bit Prescaler, a Serial Peripheral Interface

supporting S-bus, I

C-bus and IM-bus Interface,

plus two 8-bit I/O ports. The Core has independent

memory and register buses allowing a high degree

of pipelining to add to the efficiency of the code

execution speed of the extensive instruction set.

The powerful I/O capabilities demanded by micro-

controller applications are fulfilled by the ST9291

with up to 32/42 I/O lines dedicated to digital In-

put/Output. These lines are grouped into up to six

I/O Ports and can be configured on a bit basis un-

der software control to provide timing, status sig-

nals, timer inputs and outputs, analog inputs, ex-

ternal interrupts, OSD (On Screen Display) output

and serial or parallel I/O.

Three basic memory spaces are available to sup-

port this wide range of configurations: Program

Memory, Data Memory and the Register File,

which includes the control and status registers of

the on-chip peripherals.

The human interface is provided by the On Screen

Display module, this can produce up to 15 lines of

up to 34 characters from a ROM defined 128 char-

acter set. The 9x13 character can be modified by 4

different pixel sizes, with character rounding, and

formed into words with colour and format attrib-

utes.

A 14-bit VS (Voltage Synthesis) output using the

PWM (Pulse Width Modulation)/BRM (Bit Rate

Modulation) is present to generate tuning voltages

for low-mid range TV set applications. The tuning

voltage is output on one of two separate output

pins.

A 16-bit Slice Timer with an 8-bit Prescaler is also

present.

CPU

16-Bit TIMER/WATCHDOG+SPI

SLICE

TIMER

VOLTAGE

SYNTHESIS

I/O PORT 0

I/O PORT

On Screen

Display

PLL

HSYNC

PLLR

PLLF

VSYNC

I/O PORT 4

P.W.M.

Outputs

P.W.M.

D / A

Converter

I/O PORT 2

( Analog Inputs )

A / D

Converter

I/O PORT 5

( SPI )

MEMORY BUS ( Address & Data )

Note : 42 SDIP shown

VR01995E

16 k / 48 k Bytes

ROM or EPROM

(1)

384 / 640 Bytes

RAM

256 Bytes

Figure 3. ST9291 Block Diagram

Note 1. EPROM version only

ST9291

3/20

The control of TV or Satellite receiver setting can

be done by up to eight 8-bit PWM outputs, with a

frequency maximum of 23,437Hz at 8-bit resolu-

tion (INTCLK = 12MHz). Low resolutions with

higher frequency operation can be programmed.

In addition thereis a 3 channel Analog to Digital Con-

verter with integral sample and hold, fast 5.75

s con-

version time and 6-bit guaranteed resolution.

PIN DESCRIPTION

VSYNC.

Vertical Sync. Vertical video synchronisa-

tion input to OSD. Positive or negative polarity.

HSYNC.

Horizontal Sync. Horizontal video syn-

chronisation input to OSD. Positive or negative po-

larity.

PLLF.

PLL Filter input. Filter input for the OSD for

PLL feed-back.

PLLR.

PLL Resistor connection pin. For resistor

connection to select the PLL gain adjust.

RESET.

Reset (input, active low). The ST9 is initial-

ised by the Reset signal. With the deactivationof RE-

SET, program execution begins from the Program

memory location pointed to by the vector contained

in program memory locations 00h and 01h.

OSCIN, OSCOUT.

Oscillator (input and output).

These pins connect a parallel-resonant crystal

GENERAL DESCRIPTION (Continued)

(24MHz maximum), or an external source to the

on-chip clock oscillator and buffer. OSCIN is the in-

put of the oscillator inverter and internal clock gen-

erator; OSCOUT is the output of the oscillator

inverter.

. Analog V

of PLL. This pin must be tied to

externally to the ST9291.

. Main Power Supply Voltage (5V

10%)

. Digital Circuit Ground.

P0.0-P0.7,

P2.0-P2.5,

P3.0-P3.7,

P4.0-P4.7,

P5.0-P5.1 (J suffix)

P0.0-P0.7,

P1.0-P1.7,

P2.0-P2.5,

P3.0-P3.7,

P4.0-P4.7, P5.0-P5.3 (N suffix)

I/O Port Lines (In-

put/Output, TTL or CMOS compatible). 32/42 lines

grouped into I/O ports, bit programmable under

program control as general purpose I/O or as Alter-

nate functions (see next section).

P4.0 - P4.7 are high voltage (12V) open drain out-

puts. The voltage in open drain output mode for all

other I/O bits must not exceed V

I/O Port Alternate Functions.

Each pin of the I/O ports of the ST9291 may as-

sume software programmable Alternative Func-

tions as shown in the Pin Configuration Drawings.

Table 1 shows the Functions allocated to each I/O

Port pin.

ST9291

4/20

PIN DESCRIPTION (Continued)

I/O PORT

Name

Function

Alternate Function

Pin Assignment

Port.bit

9291J

9291N

P0.0

I/O

P0.1

I/O

P0.2

I/O

P0.3

I/O

P0.4

I/O

P0.5

I/O

P0.6

I/O

P0.7

I/O

P1.0

I/O

P1.1

I/O

P1.2

I/O

P1.3

I/O

P1.4

I/O

P1.5

I/O

P1.6

I/O

P1.7

I/O

P2.0

INT7

External Interrupt 7 with Schmitt Trigger

P2.1

INT5

External Interrupt 5 with Schmitt Trigger

P2.1

AIN1

A/D Analog Input 1

P2.2

INT0

External Interrupt 0

P2.2

AIN2

A/D Analog Input 2

P2.3

INT6

External Interrupt 6

P2.3

VSO1

Voltage Synthesis Output 1

P2.4

NMI

Non-Maskable Interrupt

P2.5

AIN3

A/D Analog Input 3

P2.5

VSO2

Voltage Synthesis Output 2

P3.0

Fast Blanking OSD output

P3.1

Red Video Colour OSD output

P3.2

Green Video Colour OSD output

P3.3

Blue Video Colour OSD output

Table 1.ST9291 I/O Port Alternative Function Summary

ST9291

5/20

PIN DESCRIPTION (Continued)

I/O PORT

Name

Function

Alternate Function

Pin Assignment

Port.bit

9291J

9291N

P3.4

I/O

P3.5

I/O

P3.6

I/O

P3.7

I/O

P4.0

PWM0

PWM Output 0

P4.1

PWM1

PWM Output 1

P4.2

PWM2

PWM Output 2

P4.3

PWM3

PWM Output 3

P4.4

PWM4

PWM Output 4

P4.5

PWM5

PWM Output 5

P4.6

PWM6

PWM Output 6

P4.7

PWM7

PWM Output 7

P4.7

EXTRG

A/D External Trigger

P5.0

SCK

SPI Serial Clock

(1)

P5.0

INT2

External Interrupt 2

(1)

P5.1

SDIO

I/O

SPI Serial Data Input/Output

(1 )

P5.2

I/O

P5.3

I/O

Notes.

1. The alternate functions of SCK/INT2 and SDIO may be swapped by using the SWAP Register Function.

2. Schmitt trigger options are available as a mask option for any input pin.

Table 1. ST9291 I/O Port Alternative Function Summary (Continued)

ST9291

6/20

64K

PROGRAM

MEMORY

FILE

64K

DATA

MEMORY

VA00430

Figure 1-4. Address Spaces

1 CORE DESCRIPTION

1.1 CORE ARCHITECTURE

1.1.1 INTRODUCTION

The Core or Central Processing Unit (CPU) of the

ST9 includes the 8 bit Arithmetic Logic Unit and the

16 bit Program Counter, System and User Stack

Pointers. The microcoded Instruction Set is highly

optimised for both byte (8 bit) and word (16 bit)

data, BCD and Boolean data types, with 14 ad-

dressing modes.

Three independent buses are controlled by the

Core, a 16 bit Memory bus, an 8 bit Register ad-

dressing bus and a 6 bit Interrupt/DMA bus con-

nected to the interrupt and DMA controllers in the

on-chip peripherals and the Core. This multiple bus

architecture allows a high degree of pipelining and

parallel operation, giving the ST9 its efficiency in

both numerical calculations and communication

with the on-chip peripherals.

1.1.2 ADDRESS SPACES

The ST9 has three separate address spaces:

pages of 16 bytes each, located in the on-chip

peripherals.

Data memory with up to 64K (65536) bytes

Program memory with up to 64K (65536) bytes

The Data and Program memory spaces will be ad-

dressed in further detail in section 1.3.

1.1.2.1 Register File

The Register File consists of:

224 general purpose registers R0 to R223

16 system registers in the System Group

(R224 to R239).

I/O pages depending on the configuration of

the ST9, each containing up to 16 registers,

with paging facilities based on the top group

(R240 to R255).

ST9291

7/20

ADDRESS SPACES (Continued)

PAGED REGISTERS

SYSTEM REGISTERS

255

240

239

224

223

VA00432

UP TO

64 PAGES

GENERAL

REGISTERS

PURPOSE

224

Figure 1-5. Register Grouping

PAGE 63

PAGE 5

PAGE 0

PAGE POINTER

R255

R240

R224

VA00433

Figure 1-6. Page Pointer Configuration

SYSTEM REGISTERS

GROUP D

GROUP B

GROUP C

(1100) (0011)

R192

R207

255

240

239

224

223

VR000118

R195

(R0C3h)

PAGE REGISTERS

Figure 1-7. Addressing the Register File

ST9291

8/20

1.1.2.2 Addressing Registers

All registers in the Register File and pages can be

specified by using a decimal, hex or binary ad-

dress, e.g. R231, RE7h or R11100111b is the

same register.

The registers can be referred to by their hexadeci-

mal group address, so that registers R0-R15 form

group 0, R160-R175 form group A and so on.

Working Register Addresses

The 8-bit register address is formed by 2 nibbles,

for example, for register R195 or RC3h or

R11000011, 1100 specifies the 13th group (i.e.

group C) and 0011 specifies the 3rd register in that

group.

Working registers are addressed by supplying the

least significant nibble in the instruction and adding

it to the most significant nibble found in the Regis-

ter Pointer (R233). Working register addressing is

shown in Figure 1-7.

System Registers

The 16 system registers at addresses R224 to

R239 form Group E.

The system registers are addressable using any of

the 4 register addressing modes and the most sig-

nificant nibble will, in all cases, be 14 (0Eh).

Paged Registers

There are a maximum of 64 pages each containing

16 registers. These are addressed using the regis-

ter addressing modes with the addition of the Page

Pointer register, R234. This register selects the

page to be addressed in group F and once set,

does not need to be changed if two or more regis-

ters on the same page are to be addressed in suc-

cession.

Therefore if the Page Pointer, R234, is set to 5, the

instructions

spp 5

ld R242, r4

will load the contents of working register r4 into the

third register (R242) of page 5.

These paged registers hold data and control regis-

ters related to the on-chip peripherals, and thus the

configuration depends upon the peripheral organi-

sation of each ST9 family member. i.e. pages only

exist if the peripheral exists.

Available pages are shown in Table 1-3.

1.1.2.3 Input/Output Ports

The Input/Output ports are located in two areas.

The port registers for Ports 0-5 are located at the

bottom of the System register group in locations

R224 to R229.

Each Port has three associated Control registers,

which determine the individual pin modes (I/O,

Open-Drain etc). These registers are located in

pages 2 and 3.

ADDRESS SPACES (Continued)

Hex.

Address

Decimal

Address

Function

Register File

Group

F0-FF

240-255

Paged

Registers

Group F

E0-EF

224-239

System

Registers

Group E

D0-DF

208-223

General

Purpose

Registers

Group D

C0-CF

192-207

Group C

B0-BF

176-191

Group B

A0-AF

160-175

Group A

90-9F

144-159

Group 9

80-8F

128-143

Group 8

70-7F

112-127

Group 7

60-6F

96-111

Group 6

50-5F

80-95

Group 5

40-4F

64-79

Group 4

30-3F

48-63

Group 3

20-2F

32-47

Group 2

10-1F

16-31

Group 1

00-0F

00-15

Group 0

Table 1-2. Register File Organization

ST9291

9/20

Applicable for ST9291

DEC

HEX

R255

RFF

SWAP

RESER

VSO

RFF

R254

RFE

SPI

RESER

RFE

R253

RFD

PORT 3

RESER

RFD

R252

RFC

WCR

RFC

R251

RFB

RESER

RFB

R250

RFA

T/WD

RESER

RFA

R249

RF9

PORT 2

OSD

RESER

RF9

R248

RF8

CHAR

OSD

RF8

R247

RF7

RESER

1 to 16

17 to 32

PWM

RF7

R246

RF6

R245

RF5

EXT INT PORT1

PORT 5

RF5

R244

RF4

R243

RF3

RESER

OSD

RF3

R242

RF2

SLICE

CHAR

RF2

R241

RF1

RESER

PORT 0 PORT 4 TIMER

33 to 36

A/D

RF1

R240

RF0

CONV

RF0

Table 1-3. Group F Peripheral Organization

ADDRESS SPACES (Continued)

ST9291

10/20