SIGNALLING SYSTEM 7 LINK CONTROLLER

MK50H27

Signalling System 7

Link Controller

SECTION 1 - FEATURES

Complete Level 2 Implementation of SS7.

Compatible with 1988 CCITT, AT&T, ANSI,

and Bellcore Signalling System Number 7 link

level protocols.

Optional operation to comply with Japanese

TTC JT-Q703 specification requirements

Pin-for-pin and architecturally compatible with

MK50H25 (X.25/LAPD), MK50H29 (SDLC),

and MK50H28(Frame Relay).

System clock rates up to 33 MHz (MK50H27 -

33), or 25 MHz (MK50H27 - 25).

Data rate up to 4 Mbps continuous for SS7

protocol processing, 20 Mbps for transparent

HDLC mode, or up to 51 Mbps bursted

(gapped data clocks, non-continuous data).

On chip DMA control with programmable burst

length.

DMA transfer rate of up to 13.3 Mbytes/sec us-

ing optional 5 SYSCLK DMA cycle (150 nS) at

33 MHz SYSCLK.

Buffer Management includes:

- Initialization Block

- Separate Receive and Transmit Rings

- Variable Descriptor Ring and Window Sizes.

Selectable BEC or PCR retransmission meth-

ods, including forced retransmission for PCR.

Handles all 7 SS7 Timers, plus the additional

Signal Unit interval timers for Japanese SS7.

Handles all SS7 frame formatting:

- Zero bit insert and delete

- FCS generation and detection

- Frame delimiting with flags

Programmable minimum Signal Unit spacing

(number of flags between SU’s)

Handles all sequencing and link control.

Selectable FCS of 16 or 32 bits.

Testing Facilities:

- Internal Loopback

- Silent Loopback

- Optional Internal Data Clock Generation

- Self Test.

Programmable for full or half duplex operation

Programmable Watchdog Timers for RCLK

and TCLK (to detect absence of data clocks)

Available in 52 pin PLCC, 84 pin PLCC(for use

with external ROM), or 48 pin DIP packages.

SECTION 2 - INTRODUCTION

The SGS - Thomson SS7 Signalling Link Control-

ler (MK50H27) is a VLSI semiconductor device

which provides a complete level 2 data communi-

cation control conforming to the CCITT, ANSI,

BELLCORE, and AT&T versions of SS7, as well

as options to allow conformance to TTC JT-Q703

(Japanese SS7). This includes signal unit format-

ting, transparency (so-called ”bit-stuffing”), error

recovery by two types of

retransmission, error

monitoring, sequence number control, link status

control, and fill in signal unit generation.

One of the outstanding features of the MK50H27

is its buffer management which includes on-chip

DMA. This feature allows users to handle multi-

ple MSU’s of receive and transmit data at a time.

(A conventional data link control chip plus a sepa-

rate DMA chip would handle data for only a single

block at a time.) The MK50H27 will move multiple

blocks of receive and transmit data directly into

September 1997

DIP48

PLCC 52

1/56

INTRODUCTION (Continued)

and out of memory through the Host’s bus.

possible system configuration for the MK50H27 is

shown in figure 1.

For added flexibility a transparent mode provides

an HDLC transport mechanism without link layer

support. In this mode no protocol processing is

done, all data received between opening flag and

CRC is written to the shared memory buffer and it

is up to the user to take care of the upper level

software.

The MK50H27 may be used with any of several

popular microprocessors, such as: 68040 ...

68000, 6800, Z8000, Z80, 80486 ... 8086, i960,

etc.

The MK50H27 may be operated in either full or

half duplex mode. In half duplex mode, the RTS

and CTS modem control pins are provided. In full

duplex mode, these pins become user program-

mable I/O pins. All signal pins on the MK50H27

are TTL compatible. This has the advantage of

making the MK50H27 independent of the physical

interface. As shown in figure 1, line drivers and

receivers are used for electrical connection to the

physical layer.

VSS-GND

DAL07

DAL06

DAL05

DAL04

DAL03

DAL02

DAL01

DAL00

READ

INTR

DALI

DALO

DAS

BMO, BYTE, BUSREL

BMI, BUSAKO

HOLD, BUSRQ

ALE, AS

ADR

READY

RESET

VSS-GND

HLDA

TCLK

A18

A19

A20

A21

A22

A23

DSR, CTS

SYSCLK

RCLK

DTR, RTS

VCC (+5V)

DAL08

DAL09

DAL10

DAL11

DAL12

DAL13

DAL14

DAL15

A16

A17

DIP48 PIN CONNECTION (Top view)

MK50H27

2/56

SIGNAL NAME

PIN(S)

TYPE

DESCRIPTION

DAL<15:00>

2-9

40-47

[2-10

44-51]

IO/3S

The time multiplexed Data/Address bus. During the address portion of a

memory transfer, DAL<15:00> contains the lower 16 bits of the memory

address.

During the data portion of a memory transfer, DAL<15:00> contains the read

or write data, depending on the type of transfer.

READ

[11]

IO/3S

READ indicates the type of operation that the bus controller is performing

during a bus transaction. READ is driven by the MK50H27 only while it is the

BUS MASTER. READ is valid during the entire bus transaction and is

tristated at all other times.

MK50H27 as a Bus Slave :

READ = HIGH - Data is placed on the DAL lines by the chip.

READ = LOW - Data is taken off the DAL lines by the chip.

MK50H27 as a Bus Master :

READ = HIGH - Data is taken off the DAL lines by the chip.

READ = LOW - Data is placed on the DAL lines by the chip.

INTR

[12]

O/OD

INTERRUPT is an attention interrupt line that indicates that one or more of

the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.

INTERRUPT is enabled by CSR0<09>, INEA=1.

DALI

[13]

O/3S

DAL IN is an external bus transceiver control line. DALI is driven by the

MK50H27 only while it is the BUS MASTER. DALI is asserted by the

MK50H27 when it reads from the DAL lines during the data portion of a

READ transfer. DALI is not asserted during a WRITE transfer.

DALO

[14]

O/3S

DAL OUT is an external bus transceiver control line. DALO is driven by the

MK50H27 only while it is the BUS MASTER. DALO is asserted by the

MK50H27 when it drives the DAL lines during the address portion of a READ

transfer or for the duration of a WRITE transfer.

DAS

[15]

IO/3S

DATA STROBE defines the data portion of a bus transaction. By definition,

data is stable and valid at the low to high transition of DAS. This signal is

driven by the MK50H27 while it is the BUS MASTER. During the BUS

SLAVE operation, this pin is used as an input. At all other times the signal is

tristated.

BMO

BYTE

BUSREL

[16]

IO/3S

I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set

to a one, pin 15 becomes input BUSREL and is used by the host to signal

the MK50H27 to terminate a DMA burst after the current bus transfer has

completed. If bit 06 is clear then pin 15 is an output and behaves as

described below for pin 16.

BM1

BUSAKO

[18]

O/3S

Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).

If CSR4<00> BCON = 0,

I/O PIN 15 = BMO (O/3S)

I/O PIN 16 = BM1 (O/3S)

BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written

during this bus transaction. MK50H27 drives these lines only as a Bus

Master. MK50H27 ignores the BM lines when it is a Bus Slave.

Byte selection is done as outlined in the following table.

BM1

BM0

TYPE OF TRANSFER

LOW

ENTIRE WORD

LOW

HIGH

UPPER BYTE

(DAL<15:08>)

HIGH

LOW

LOWER BYTE

(DAL<07:00>)

HIGH

NONE

TAble 1 - PIN DESCRIPTION

LEGEND:

Input only

Output only

Input / Output

3-State

Open Drain (no internal pull-up)

Note:

Pin out for 52 pin PLCC is shown in brackets.

MK50H27

4/56

Table 1: PIN DESCRIPTION (continued)

SIGNAL NAME

PIN(S)

TYPE

DESCRIPTION

If CSR4<00> BCON = 1,

I/O PIN 15 = BYTE (O/3S)

I/O PIN 16 = BUSAKO (O)

Byte selection is done using the BYTE line and DAL<00> latched during the

address portion of the bus transaction. MK50H27 drives BYTE only as a Bus

Master and ignores it when a Bus Slave. Byte selection is done as outlined

in the following table.

BYTE

DAL<00>

TYPE OF TRANSFER

LOW

ENTIRE WORD

LOW

HIGH

ILLEGAL CONDITION

HIGH

LOW

LOWER BYTE

HIGH

UPPER BYTE

BUSAKO is a bus request daisy chain output. If MK50H27 is not requesting

the bus and it receives HLDA, BUSAKO will be driven low. If MK50H27 is

requesting the bus when it receives HLDA, BUSAKO will remain high

Note: All transfers are entire word unless the MK50H27 is configured for 8 bit

operation.

HOLD

BUSRQ

[19]

IO/OD

Pin 17 is configured through bit 0 of CSR4.

If CSR4<00> BCON = 0,

I/O PIN 17 = HOLD

HOLD request is asserted by MK50H27 when it requires a DMA cycle, if

HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is

held low for the entire ensuing bus transaction.

If CSR4<00> BCON = 1,

I/O PIN 17 = BUSRQ

BUSRQ is asserted by MK50H27 when it requires a DMA cycle if the prior

state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low

for the entire ensuing bus transaction.

ALE

[20]

O/3S

The active level of ADDRESS STROBE is programmable through CSR4.

The address portion of a bus transfer occurs while this signal is at its

asserted level. This signal is driven by MK50H27 while it is the BUS

MASTER. At all other times, the signal is tristated.

If CSR4<01> ACON = 0,

I/O PIN 18 = ALE

ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define

the address portion of the transfer. As ALE, the signal transitions from high

to low during the address portion of the transfer and remains low during the

data portion.

If CSR4<01> ACON = 1,

I/O PIN 18 = AS

As AS, the signal pulses low during the address portion of the bus transfer.

The low to high transition of AS can be used by a slave device to strobe the

address into a register.

AS is effectively the inversion of ALE.

HLDA

[21]

HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in

response to MK50H27’s assertion of HOLD, the MK50H27 is the Bus

Master. HLDA should be deasserted ONLY after HOLD has been released

by the MK50H27.

[22]

CHIP SELECT indicates, when low, that the MK50H27 is the slave device

for the data transfer. CS must be valid throughout the entire transaction.

ADR

[23]

ADDRESS selects the Register Address Port or the Register Data Port. It

must be valid throughout the data portion of the transfer and is only used by

the chip when CS is low.

ADR

PORT

LOW

HIGH

READY

[24]

IO/OD

When the MK50H27 is a Bus Master, READY is an asynchronous

acknowledgement from the bus memory that memory will accept data in a

WRITE cycle or that memory has put data on the DAL lines in a READ cycle.

MK50H27

5/56

Table 1: PIN DESCRIPTION (continued)

SIGNAL NAME

PIN(S)

TYPE

DESCRIPTION

As a Bus Slave, the MK50H27 asserts READY when it has put data on the

DAL lines during a READ cycle or is about to take data from the DAL lines

during a WRITE cycle. READY is a response to DAS and it will be released

after DAS or CS is negated.

RESET

[25]

RESET is the Bus signal that will cause MK50H27 to cease operation, clear

its internal logic and enter an idle state with the Stop bit of CSR0 set.

TCLK

[28]

TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes on

the falling edge of TCLK. The frequency of TCLK may not be greater than

the frequency of SYSCL

DTR

RTS

[29]

DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin

26 is configurable through CSR5. This pin can be programmed to behave as

output RTS or as programmable IO pin DTR. If configured as RTS, the

MK50H27 will assert this pin if it has data to send and throughout the

transmission of a signal unit.

RCLK

[30]

RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on

the rising edge of RCLK. The frequency of RCLK may not be greater than

the frequency of SYSCLK.

SYSCLK

[31]

SYSTEM CLOCK. System clock used for internal timing of the MK50H27.

SYSCLK should be a square wave, of frequency up to 33 MHz.

[32]

TRANSMIT DATA. Transmit serial data output.

DSR

CTS

[33]

DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is

configurable through CSR5. This pin can be programmed to behave as input

CTS or as programmable IO pin DSR. If configured as CTS, the MK50H27

will transmit all ones while CTS is high.

[34]

RECEIVE DATA. Received serial data input.

A<23:16>

32-39

[37-43]

O/3S

Address bits <23:16> used in conjunction with DAL<15:00> to produce a 24

bit address. MK50H27 drives these lines only as a Bus Master. A23-A20

may be driven continuously as described in the CSR4<7> BAE bit.

VSS-GND

1,24

[1,26]

Ground Pins

VCC

[52]

Power Supply Pin

+5.0 VDC + 5%

SECTION 3

OPERATIONAL DESCRIPTION

The SGS-Thomson MK50H27 Multi-Logical Link

Communications Controller device is a VLSI prod-

uct intended for high performance data communi-

cation applications requiring SDLC link level con-

trol. The

MK50H27 will

perform all

frame

formatting, such as: frame delimiting with flags,

FCS (CRC) generation and detection, and zero

bit insertion and deletion for transparency. The

MK50H27 also handles all supervisory (S) and

unnumbered (U) frames (see Tables A & B). The

MK50H27 also includes a buffer management

mechanism that allows the user to transmit and/or

receive multiple frames for each active channel

or DLCI. Contained in the buffer management is

an on-chip dual channel DMA: one channel for re-

ceive and one channel for transmit.

The MK50H27 can be used with any popular 16

or 8 bit microprocessor. A possible system con-

figuration for the MK50H27 is shown in Figure 1.

This document assumes that the processor has a

byte addressable memory organization.

The MK50H27 will move multiple blocks of re-

ceive and transmit data directly in and out of

memory through the Host’s bus.

The MK50H27 may be operated in full or half du-

plex mode.

In half duplex mode the RTS and

CTS modem control pins are provided. In full du-

plex mode, these pins become user programma-

ble I/O pins.

All signal pins on the MK50H27 are TTL compat-

ible.

This has the advantage of making the

MK50H27 independent of the physical interface.

As shown in Fig. 1, line drivers and receivers are

used for electrical connection to the physical

layer.

MK50H27

6/56

3.1 Functional Blocks

Refer to the block diagram in Figure 2.

The MK50H27 is primarily initialized and control-

led through six 16-bit Control and Status Regis-

ters (CSR0 thru CSR5). The CSR’s are accessed

through two bus addressable ports, the Register

Address Port (RAP), and the Register Data Port

(RDP). The MK50H27 may also generate an in-

terrupt(s) to the Host. These interrupts are en-

abled and disabled through CSR0.

The on-chip microcontroller is used to control the

movement of parallel receive and transmit data,

and to handle the Address field filtering.

3.1.1 Microcontroller

The microcontroller controls all of the other blocks

of the MK50H27. The microcontroller performs

frame processing and protocol processing. All

primitive processing and generation is also done

here. The microcode ROM contains the control

program of the microcontroller.

3.1.2 Receiver

Serial receive data comes into the Receiver (Fig-

ure 2). The Receiver is responsible for:

1. Leading and trailing flag detection.

2. Deletion of zeroes inserted for transparency.

3. Detection of idle and abort sequences.

4. Detection of good & bad CK (ChecK bit seq.)

5. Monitoring Receiver FIFO status.

6. Detection of Receiver Over-Run.

7. Odd byte detection.

NOTE: If frames are received that have an odd

number of bytes then the last byte of the

frame is said to be an odd byte.

8. Detection of non-octet aligned frames. Such

frames are treated as invalid.

3.1.3 Transmitter

The Transmitter is responsible for:

1. Serialization of outgoing data.

2. Generating and appending the CK (CRC).

3. Framing outgoing frame with flags.

4. Zero bit insertion for transparency.

5. Transmitter Under-Run detection.

6. Transmission of odd byte.

7. RTS/CTS control.

3.1.4 Check Bit Sequence or Cyclic

Redundancy Check

The CK (CRC) on the transmitter or receiver may

be either 16 bit or 32 bit, and is user selectable.

For full duplex operation, both the receiver and

transmitter have individual CK computation cir-

cuits. The characteristics of the CK are:

Transmitted Polarity: Inverted

Transmitted Order: High Order Bit First

Pre-set Value: All 1’s

Polynomial 16 bit:

+ X

+ 1

Remainder 16 bit (if received correctly):

High order bit-->0001 1101 0000 1111

Polynomial 32 bit:

+ X

+ X + 1

Remainder 32 bit (if received correctly):

high order bit--> 1100 0111 0000 0100

1101 1101 0111 1011

3.1.5 Receive FIFO

The Receive FIFO buffers the data received by

the receiver. This performs two major functions.

First, it resynchronizes the data from the receive

clock to the system clock. Second, it allows the

microcontroller time to finish whatever it may be

doing before it has to process the received data.

The receive FIFO holds the data from the receiver

without interrupting the microcontroller for service

until it contains enough data to reach the water-

mark level, or an end of frame is received. This

watermark level can be programmed in CSR4

(FWM) to occur when the FIFO contains at least

18 or more bytes; 34 or more bytes; or 50 or

more bytes. This programmability , along with the

programmable burst length of the DMA controller,

enables the user to define how often and for how

long the MK50H27 must use the host bus. For

more information, see CSR4.

For example, if the watermark level is set at 34

bytes and the burst length is limited to 8 word

transfers at a time, the MK50H27 will request

control of the host bus as soon as 34 bytes are

received and again after every 16 subsequent

bytes.

3.1.6 Transmit FIFO

The Transmit FIFO buffers the data to be trans-

mitted by the MK50H27. This also performs two

major functions. First, it resynchronizes the data

from the system clock to the transmit clock. Sec-

ond, it allows the microcontroller and DMA con-

troller to burst read data from the host’s memory

buffers; making both the MK50H27 and the host

bus more efficient.

MK50H27

9/56

The transmit FIFO has a watermark scheme simi-

lar to the one described for the receive FIFO

above, and uses the same FWM value selections

in CSR4 for the watermark. Once filled to within

FWM of being full (by DMA from TX buffer in

shared memory), the transmit FIFO will not inter-

rupt the microcontroller until it empties enough to

fall below the watermark level.

3.1.7 DMA Controller

The MK50H27 has an on-chip DMA Controller cir-

cuit. This allows it to access memory without re-

quiring host software intervention. Whenever the

MK50H27 requires access to the host memory it

will negotiate for mastership of the bus.

Upon

gaining control of the bus the MK50H27 will begin

transferring data to or from memory.

The

MK50H27 will perform memory transfers until

either it has nothing more to transfer, it has

reached its DMA burst limit (user programmable),

or the BUSREL pin is driven low. In any case, it

will complete all bus transfers before releasing

bus mastership back to the host.

If during a

memory transfer, the memory does not respond

within 256 SCLK cycles, the MK50H27 will re-

lease ownership of the bus immediately and the

MERR bit will be set in CSR0. The DMA burst

limit can be programmed by the user through

CSR4. In 16 bit mode the limit can be set to 1

word, 8 words, or unlimited word transfers. In 8

bit mode,it can be set to 2 bytes, 16 bytes, or un-

limited byte transfers. For high speed data lines

(i.e. > 1 Mbps) a burst limit of 8 words or 16 bytes

is suggested to allow maximum throughput.

The byte ordering of the DMA transfers can be

programmed to account for differences in proces-

sor architectures or host programming languages.

Byte ordering can be programmed separately for

data and control information. Data information is

defined as all contents of data buffers; control in-

formation is defined as anything else in the

shared memory space (i.e. initialization block, de-

scriptors, etc). For more information see section

4.1.2.5 on control status register 4.

3.1.8 Bus Slave Circuitry

The MK50H27 contains a bank of internal con-

trol/status registers (CSR0-5) which can be ac-

cessed by the host as a peripheral. The host can

read or write to these registers like any other bus

slave. The contents of these registers are listed

in Section 4 and bus signal timing is described in

Figures 9 and 10.

3.2 Buffer Management Overview

Refer to Fig. 3.

3.2.1 Initalization Block

Chip initialization information is located in a block

of memory called the Initialization Block. The In-

itialization Block consists of 200 contiguous words

of memory starting on a word boundary. This

memory is assembled by the HOST, and is ac-

cessed by the MK50H27 during initialization. The

Initialization Block is comprised of:

A. Mode of Operation.

B. Counter/Timer Preset Values.

C. Protocol Parameters or Options

D. Location and size of Receive and Transmit De-

scriptor Rings.

E. Optional Transmit Window SIze Value

F. Location of Status Buffer.

G. Optional JT-Q703 Signal Unit Interval Timer

Values

H. Statistics and Error Counters.

3.2.2 The Circular Queue

The basic organization of the buffer management

is a circular queue of tasks in memory called de-

scriptor rings. There are separate rings to de-

scribe the transmit and receive operations. Up to

128 buffers may be queued-up on a descriptor

ring awaiting execution by the MK50H27. The

descriptor ring has a descriptor assigned to each

buffer. Each descriptor holds a pointer for the

starting address of the buffer, and holds a value

for the length of the buffer in bytes.

Each descriptor also contains two control bits

called OWNA and OWNB, which denote whether

the MK50H27, the HOST, or an I/O ACCELERA-

TION PROCESSOR ( if present ) ”owns” the buff-

er. For transmit, when the MK50H27 owns the

buffer, the MK50H27 is allowed and commanded

to transmit the buffer. When the MK50H27 does

not own the buffer, it will not transmit that buffer.

For receive, when the MK50H27 owns a buffer, it

may place received data into that buffer. Con-

versely, when the MK50H27 does not own a re-

ceive buffer, it will not place received data into

that buffer.

The MK50H27 buffer management mechanism

will handle frames which are longer than the

length of an individual buffer. This is done by a

chaining method which utilizes multiple buffers.

The MK50H27 tests the next descriptor in the de-

scriptor ring in a ”look ahead” manner.

If the

frame is too long for one buffer, the next buffer

will be used after filling the first buffer; that is,

”chained”. The MK50H27 will then ”look ahead”

to the next buffer, and chain that buffer if neces-

sary, and so on.The operational parameters for

the buffer management are defined by the user in

the initialization block. The parameters defined

include the basic mode of operation, protocol op-

tions, the number of entries for the transmitter

MK50H27

10/56

and receiver descriptor rings, etc.

The starting

address for the Initialization block, IADR, is de-

fined in the CSR2 and CSR3 registers inside the

MK50H27.

3.2.3 Signal Unit Repertoire

The frame format supported by the MK50H27 is

shown in Table A.

Each signal unit (SU) may

consist of a programmable number of leading flag

patterns (01111110), Backward Sequence Num-

ber, Backward Indicator Bit, Forward Sequence

Number, Forward Indicator Bit, Lenght Indicator

Field, followed by Signalling Information Octet,

Service Information Field, or Status Field, de-

pending on SU type, and then ended with a CK

(CRC) of either 16 or 32 bits, and a trailing flag

pattern. The number of leading flags transmitted

is programmable through the Mode Register in

the Initialization Block. Received signal units may

have as few as one flag between adjacent signal

units

The symbols and definitions for the signal unit

types handled by the MK50H27 are:

TABLE A - MK50H27 Signal Unit Repertoire

NAME

DEFINITION

MSU

Message Signal Unit

LSSU

Link Status Signal Unit

FISU

Fill In Signal Unit

Flag Sequence (01111110)

FSN

Forward Sequence Number

BSN

Backward Sequence Number

FIB

Forward Indicator Bit

BIB

Backward Indicator Bit

Lenght Indicator

Reserved - programmed as zeroes

PRI

Priority Indication (JT-Q703 only)

SIO

Signalling Information Octe

SIF

Service Information Field

Status Field

Check bit Sequence (CRC)

MK50H27

11/56