SG2525A
SG3525A
REGULATING PULSE WIDTH MODULATORS
.
8 TO 35 V OPERATION
.
5.1 V REFERENCE TRIMMED TO
±
1 %
.
100 Hz TO 500 KHz OSCILLATOR RANGE
.
SEPARATE OSCILLATOR SYNC TERMINAL
.
ADJUSTABLE DEADTIME CONTROL
.
INTERNAL SOFT-START
.
PULSE-BY-PULSE SHUTDOWN
.
INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
.
LATCHING PWM TO PREVENT MULTIPLE
PULSES
.
DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION
The SG3525Aseries of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to
±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor betweenthe C
T
andthe dischargeterminals
provide a wide range of dead time ad-
justment.
Thesedevicesalso featurebuilt-insoft-startcircuitry
with only an external timing capacitor required. A
shutdownterminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltagelockout which keepsthe out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525Aoutput stage features NOR logic, giving a
LOW output for an OFF state.
DIP16
16(Narrow)
Type
Plastic DIP
SO16
SG2525A
SG2525AN
SG2525AP
SG3525A
SG3525AN
SG3525AP
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
®
June 2000
1/12
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
i
Supply Voltage
40
V
V
C
Collector Supply Voltage
40
V
I
OSC
Oscillator Charging Current
5
mA
I
o
Output Current, Source or Sink
500
mA
I
R
Reference Output Current
50
mA
I
T
Current through C
T
Terminal
Logic Inputs
Analog Inputs
5
– 0.3 to + 5.5
– 0.3 to V
i
mA
V
V
P
tot
Total Power Dissipation at T
amb
= 70
°
C
1000
mW
T
j
Junction Temperature Range
– 55 to 150
°
C
T
stg
Storage Temperature Range
– 65 to 150
°
C
T
op
Operating Ambient Temperature : SG2525A
SG3525A
– 25 to 85
0 to 70
°
C
°
C
THERMAL DATA
Symbol
Parameter
SO16
DIP16
Unit
R
th j-pins
R
th j-amb
R
th j-alumina
Thermal Resistance Junction-pins
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Junction-alumina (*)
Max
50
50
80
°
C/W
°
C/W
°
C/W
* Thermalresistance junction-alumina with the device soldered on themiddle ofan alumina supporting substrate measuring 15
×
20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
SG2525A-SG3525A
2/12
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol
Parameter
Test Conditions
SG2525A
SG3525A
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
REFERENCE SECTION
V
REF
Output Voltage
T
j
= 25
°
C
5.05
5.1
5.15
5
5.1
5.2
V
∆
V
REF
Line Regulation
V
i
= 8 to 35 V
10
20
10
20
mV
∆
V
REF
Load Regulation
I
L
= 0 to 20 mA
20
50
20
50
mV
∆
V
REF
/
∆
T* Temp. Stability
Over Operating Range
20
50
20
50
mV
*
Total Output Variation
Line, Load and
Temperature
5
5.2
4.95
5.25
V
Short Circuit Current
V
REF
= 0 T
j
= 25
°
C
80
100
80
100
mA
*
Output Noise Voltage
10 Hz
≤
f
≤
10 kHz,
T
j
= 25
°
C
40
200
40
200
µ
Vrms
∆
V
REF
*
Long Term Stability
T
j
= 125
°
C, 1000 hrs
20
50
20
50
mV
OSCILLATOR SECTION * *
*,
•
Initial Accuracy
T
j
= 25
°
C
±
2
±
6
±
2
±
6
%
*,
•
Voltage Stability
V
i
= 8 to 35 V
±
0.3
±
1
±
1
±
2
%
∆
f/
∆
T*
Temperature Stability
Over Operating Range
±
3
±
6
±
3
±
6
%
f
MIN
Minimum Frequency
R
T
= 200 K
Ω
C
T
= 0.1
µ
F
120
120
Hz
f
MAX
Maximum Frequency
R
T
= 2 K
Ω
C
T
= 470 pF
400
400
KHz
Current Mirror
I
RT
= 2 mA
1.7
2
2.2
1.7
2
2.2
mA
*,
•
Clock Amplitude
3
3.5
3
3.5
V
*,
•
Clock Width
T
j
= 25
°
C
0.3
0.5
1
0.3
0.5
1
µ
s
Sync Threshold
1.2
2
2.8
1.2
2
2.8
V
Sync Input Current
Sync Voltage = 3.5 V
1
2.5
1
2.5
mA
ERROR AMPLIFIER SECTION (V
CM
= 5.1 V)
V
OS
Input Offset Voltage
0.5
5
2
10
mV
I
b
Input Bias Current
1
10
1
10
µ
A
I
os
Input Offset Current
1
1
µ
A
DC Open Loop Gain
R
L
≥
10 M
Ω
60
75
60
75
dB
*
Gain Bandwidth
Product
G
v
= 0 dB
T
j
= 25
°
C
1
2
1
2
MHz
*,
DC Transconduct.
30 K
Ω ≤
R
L
≤
1 M
Ω
T
j
= 25
°
C
1.1
1.5
1.1
1.5
ms
Output Low Level
0.2
0.5
0.2
0.5
V
Output High Level
3.8
5.6
3.8
5.6
V
CMR
Comm. Mode Reject.
V
CM
= 1.5 to 5.2 V
60
75
60
75
dB
PSR
Supply Voltage
Rejection
V
i
= 8 to 35 V
50
60
50
60
dB
SG2525A-SG3525A
3/12
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
SG2525A
SG3525A
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
PWM COMPARATOR
Minimum Duty-cycle
0
0
%
•
Maximum Duty-cycle
45
49
45
49
%
•
Input Threshold
Zero Duty-cycle
0.7
0.9
0.7
0.9
V
Maximum Duty-cycle
3.3
3.6
3.3
3.6
V
*
Input Bias Current
0.05
1
0.05
1
µ
A
SHUTDOWN SECTION
Soft Start Current
V
SD
= 0 V, V
SS
= 0 V
25
50
80
25
50
80
µ
A
Soft Start Low Level
V
SD
= 2.5 V
0.4
0.7
0.4
0.7
V
Shutdown Threshold
To outputs, V
SS
= 5.1 V
T
j
= 25
°
C
0.6
0.8
1
0.6
0.8
1
V
Shutdown Input Current V
SD
= 2.5 V
0.4
1
0.4
1
mA
*
Shutdown Delay
V
SD
= 2.5 V T
j
= 25
°
C
0.2
0.5
0.2
0.5
µ
s
OUTPUT DRIVERS (each output) (V
C
= 20 V)
Output Low Level
I
sink
= 20 mA
0.2
0.4
0.2
0.4
V
I
sink
= 100 mA
1
2
1
2
V
Output High Level
I
source
= 20 mA
18
19
18
19
V
I
source
= 100 mA
17
18
17
18
V
Under-Voltage Lockout
V
comp
and V
ss
= High
6
7
8
6
7
8
V
I
C
Collector Leakage
V
C
= 35 V
200
200
µ
A
t
r
*
Rise Time
C
L
= 1 nF, T
j
= 25
°
C
100
600
100
600
ns
t
f
*
Fall Time
C
L
= 1 nF, T
j
= 25
°
C
50
300
50
300
ns
TOTAL STANDBY CURRENT
I
s
Supply Current
V
i
= 35 V
14
20
14
20
mA
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
•
Tested at f
osc
= 40 KHz (R
T
= 3.6 K
Ω
, C
T
= 10nF, R
D
= 0
Ω
). Approximate oscillator frequency is defined by :
1
f =
C
T
(0.7 R
T
+ 3 R
D
)
.
DC transconductance (g
M
) relates to DC open-loop voltage gain (G
v
) according to the following equation : G
v
= g
M
R
L
where R
L
is the resistance
from pin 9 to ground. The minimum g
M
specification is used to calculate minimum G
v
when the error amplifier output is loaded.
SG2525A-SG3525A
4/12
TEST CIRCUIT
SG2525A-SG3525A
5/12
Figure 1 : Oscillator Charge Time vs. R
T
and C
T
.
Figure 2 : Oscillator Discharge Time vs. R
D
and C
T
.
RECOMMENDED OPERATING CONDITIONS (
•
)
Parameter
Value
Input Voltage (V
i
)
8 to 35 V
Collector Supply Voltage (V
C
)
4.5 to 35 V
Sink/Source Load Current (steady state)
0 to 100 mA
Sink/Source Load Current (peak)
0 to 400 mA
Reference Load Current
0 to 20 mA
Oscillator Frequency Range
100 Hz to 400 KHz
Oscillator Timing Resistor
2 K
Ω
to 150 K
Ω
Oscillator Timing Capacitor
0.001
µ
F to 0.1
µ
F
Dead Time Resistor Range
0 to 500
Ω
•
(
⋅
)
Range over which the device is functional and parameter limits are guaranteed.
Figure 3 : Output Saturation
Characteristics.
Figure 4 : Error Amplifier Voltage Gain and
Phase vs. Frequency.
SG2525A-SG3525A
6/12
SHUTDOWN OPTIONS (see Block Diagram)
Since both the compensation and soft-start termi-
nals (Pins 9 and 8) have current source pull-ups,
either can readily accept a pull-down signal which
only has to sink a maximum of 100
µ
A
to turn off the
outputs.This is subject to the added requirement of
discharging whatever external capacitance may be
attached to these pins.
An alternateapproachis the useof the shutdowncir-
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating
this circuit by applying a positive signal on Pin 10
performs two functions : the PWM latch is immedi-
ately set providing the fastest turn-off signal to the
outputs ; and a 150
µ
A current sink begins to dis-
charge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is termi-
nated without significant discharge of the soft-start
capacitor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting.
Holding Pin 10 high for a longer duration, however,
will ultimately discharge this external capacitor, re-
cycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup
could conceivably interrupt normal operation.
Figure 5 : Error Amplifier.
PRINCIPLES OF OPERATION
SG2525A-SG3525A
7/12
Figure 7 : Output Circuit (1/2 circuit shown).
Figure 6 : Oscillator Schematic.
SG2525A-SG3525A
8/12
Figure 10.
Figure 11.
For single-ended supplies, the driver outputs are
grounded.The V
C
terminal is switched to groundby
the totem-pole source transistors on alternate oscil-
lator cycles.
In conventional push-pull bipolar designs, forward
base drive is controlled by R
1
- R
3
. Rapid turn-off
times for the power devices are achieved with
speed-up capacitors C
1
and C
2
.
The low source impedanceof the outputdrivers pro-
vides rapid charging of Power Mos input capaci-
tance while minimizing external components.
Low power transformers can be driven directly.
Automaticreset occurs during deadtime, when both
ends of the primary winding are switched to ground.
Figure 8.
Figure 9.
SG2525A-SG3525A
9/12
DIP16
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
OUTLINE AND
MECHANICAL DATA
SG2525A-SG3525A
10/12
SO16 Narrow
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.069
a1
0.1
0.25
0.004
0.009
a2
1.6
0.063
b
0.35
0.46
0.014
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.020
c1
45
°
(typ.)
D (1)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F (1)
3.8
4
0.150
0.157
G
4.6
5.3
0.181
0.209
L
0.4
1.27
0.016
0.050
M
0.62
0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8
°
(max.)
SG2525A-SG3525A
11/12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
©
2000 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
SG2525A-SG3525A
12/12