8-BIT MICROCONTROLLER ( MCU ) WITH OTP, ROM, FASTROM, EPROM, A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM, SPI AND 20 PINS

April 1998

1/75

Rev. 2.4

ST62T53B/T60B/T63B

ST62E60B

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

AUTO-RELOAD TIMER, EEPROM AND SPI

3.0 to 6.0V Supply Operating Range

8 MHz Maximum Clock Frequency

-40 to +125

C Operating Temperature Range

Run, Wait and Stop Modes

5 Interrupt Vectors

Look-up Table capability in Program Memory

Data Storage in Program Memory:

User selectable size

Data RAM: 128 bytes

DataEEPROM:64/128bytes(none onST62T53B)

User Programmable Options

13 I/O pins, fully programmable as:

– Input with pull-up resistor

– Input without pull-up resistor

– Input with interrupt generation

– Open-drain or push-pull output

– Analog Input

6 I/O lines can sink up to 20mA to drive LEDs or

TRIACs directly

8-bit Timer/ Counter with 7-bit programmable

prescaler

8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

Digital Watchdog

8-bit A/D Converter with 7 analog inputs

8-bit Synchronous Peripheral Interface (SPI)

On-chip Clock oscillator can be driven by Quartz

Crystal Ceramic resonator or RC network

User configurable Power-on Reset

One external Non-Maskable Interrupt

ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a

parallel port).

DEVICE SUMMARY

(See end of Datasheet for Ordering Information)

PDIP20

PSO20

CDIP20W

DEVICE

OTP

(Bytes)

EPROM

(Bytes)

EEPROM

ST62T53B

1836

ST62T60B

3884

128

ST62T63B

1836

ST62E60B

3884

128

2/75

Table of Contents

ST62T53B/T60B/T63B / ST62E60B . . . . . . . . . . . . . . . . . . . . . .1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.6 Data RAM/EEPROM Bank Register (DRBR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.4.3 EEPROM Data Memory (except ST62T53B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Table of Contents

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.4

A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5.1 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.6 SPI TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

ST62P53B/P60B/P63B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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ST62T53B/T60B/T63B ST62E60B

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The

ST62T53B,

ST62T60B,

ST62T63B

and

ST62E60B devices are low cost members of the

ST62xx 8-bit HCMOS family of microcontrollers,

which is targeted at low to medium complexity ap-

plications. All ST62xx devices are based on a

building block approach: a common core is sur-

rounded by a number of on-chip peripherals.

The ST62E60B is the erasable EPROM version of

the ST62T60B device, which may be used to em-

ulate the ST62T53B, ST62T60B and ST62T63B

devices, as well as the respective ST6253B,

ST6260B and ST6263B ROM devices.

OTP and EPROM devices are functionally identi-

cal. The ROM based versions offer the same func-

tionality selecting as ROM options the options de-

fined in the programmable option byte of theOTP/

EPROM versions.

OTP devices offer all the advantages of user pro-

grammability at low cost, which make them the

ideal choice in a wide range of applications where

frequent code changes, multiple code versions or

last minute programmability are required.

These compact low-cost devices feature a Timer

comprising an 8-bit counter and a 7-bit program-

mable prescaler, an 8-bit Auto-Reload Timer,

EEPROM data capability (except ST62T53B), a

serial port communication interface, an 8-bit A/D

Converter with 7 analog inputs and a Digital

Watchdog timer, making them well suited for a

wide range of automotive, appliance and industrial

applications.

Figure 1. Block Diagram

TEST

NMI

INTER RUPT

PROGRAM

STA CK LEVEL 1

STA CK LEVEL 2

STA CK LEVEL 3

STA CK LEVEL 4

STA CK LEVEL 5

STA CK LEVEL 6

POWER

SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

8-BIT

A/D CONVERTE R

PA0..PA3 / Ain

PB0..PB3 / 20 mA Sink

OSCin OSCout

RESET

WATCHDOG

MEMORY

PB6 / ARTimin / 20 mA Sink

PORT C

PC2 / Sin / Ain

PC3 / Sout / Ain

SPI (SERIAL

PERIPHERAL

INTERFACE )

AUTORELOAD

TIMER

PC4 / Sck / Ain

PB7 / ARTimout / 20 mA Sink

128 Bytes

1836 byt es OTP

3884 byt es OTP

3884 bytes EPROM

(ST62T53B,T63B)

(ST62T60B)

(ST62E60B)

DATA EEPROM

64 Bytes

12 8 Bytes

(ST62T60B/E60B)

(ST62T63B)

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ST62T53B/T60B/T63B ST62E60B

1.2 PIN DESCRIPTIONS

and V

. Power is supplied to the MCU via

these two pins. V

is the power connection and

is the ground connection.

OSCin and OSCout. These pins are internally

connected to the on-chip oscillator circuit. A quartz

crystal, a ceramic resonator or an external clock

signal can be connected between these two pins.

The OSCin pin is the input pin, the OSCout pin is

the output pin.

RESET. The active-low RESET pin is used to re-

start the microcontroller.

TEST/V

. The TEST must be held at V

for nor-

mal operation. If TEST pin is connected to a

+12.5V level during the reset phase, the EPROM/

OTP programming Mode is entered.

NMI. The NMI pin provides the capability for asyn-

chronous interruption, by applying an external non

maskable interrupt to the MCU. The NMI input is

falling edge sensitive.It is provided with an on-chip

pullup resistor and Schmitt trigger characteristics.

PA0-PA3. These 4 lines are organized as one I/O

port (A). Each line may be configured under soft-

ware control as inputs with or without internal pull-

up resistors, interrupt generating inputs with pull-

up resistors, open-drain or push-pull outputs, ana-

log inputs for the A/D converter.

PB0-PB3. These 4 lines are organized as one I/O

port (B). Each line may be configured under soft-

ware control as inputs with or without internal pull-

up resistors, interrupt generating inputs with pull-

up resistors, open-drain or push-pull outputs.

PB0-PB3 can also sink 20mA for direct LED

driving.

PB6/ARTIMin, PB7/ARTIMout. These pins are ei-

ther Port B I/O bits or the Input and Output pins of

the AR TIMER. To be used as timer input function

PB6 has to be programmed as input with or with-

out pull-up. A dedicated bit in the AR TIMER Mode

Control Register sets PB7 as timer output function.

PB6-PB7 can also sink 20mA for direct LED driv-

ing.

PC2-PC4. These 3 lines are organized as one I/O

port (C). Each line may be configured under soft-

ware control as input with or without internal pull-

up resistor, interrupt generating input with pull-up

resistor, analog input for the A/D converter, open-

drain or push-pull output.

PC2-PC4 can also be used as respectively Data

in, Data out and Clock I/O pins for the on-chip SPI

to carry the synchronous serial I/O signals.

Figure 2. ST62T53/T60B/T63B/E60B Pin

Configuration

PB0

PB1

/TEST

PB2

PB3

Ain/PA0

PC2 / Sin / Ain

RESET

PA1/Ain

ARTIMin/PB6

ARTIMout/PB7

PC3 / Sout / Ain

PC4 / Sck / Ain

NMI

OSCin

OSCout

PA2/Ain

PA3/Ain

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ST62T53B/T60B/T63B ST62E60B

MEMORY MAP (Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be

executed, the data required for immediate ad-

dressing mode instructions, the reserved factory

test area and the user vectors. Program Space is

addressed via the 12-bit Program Counter register

(PC register).

1.3.2.1 Program Memory Protection

The Program Memory in OTP or EPROM devices

can be protected against external readout of mem-

ory by selecting the READOUT PROTECTION op-

tion in the option byte.

Figure 4. ST62E60B/T60B Program

Memory Map

In the EPROM parts, READOUT PROTECTION

option can be disactivated only by U.V. erasure

that also results into the whole EPROM context

erasure.

Note: Once the Readout Protection is activated, it

is no longer possible, even for SGS-THOMSON,

to gain access to the OTP contents. Returned

parts with a protection set can therefore not be ac-

cepted.

Figure 5. ST62T53B/T63B Program

Memory Map

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP/EPROM)

3872 BYTES

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

0080h

(*) Reserved areas should be filled with 0FFh

007Fh

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP)

1824 BYTES

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

087Fh

(*) Reserved areas should be filled with 0FFh

0880h

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ST62T53B/T60B/T63B ST62E60B

MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary

for processing the user program. This space com-

prises the RAM resource, the processor core and

peripheral registers, as well as read-only data

such as constants and look-up tables in OTP/

EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program

memory, which also accommodates the Program

Space. The program memory consequently con-

tains the program code to be executed, as well as

the constants and look-up tables required by the

application.

The Data Space locations in which the different

constants and look-up tables are addressed by the

processor core may be thought of as a 64-byte

window through which it is possible to access the

read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T53B, T60B, T63B and ST62E60B devic-

es, the data space includes 60 bytes of RAM, the

accumulator (A), the indirect registers (X), (Y), the

short direct registers (V), (W), the I/O port regis-

ters, the peripheral data and control registers, the

interrupt option register and the Data ROM Win-

dow register (DRW register).

Additional RAM and EEPROM pages can also be

addressed using banks of 64 bytes located be-

tween addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which

are used to stack subroutine and interrupt return

addresses, as well as the current program counter

contents.

Table 1. Additional RAM/EEPROM Banks

Table 2. ST62T53B, T60B, T63B and ST62E60B

Data Memory Space

Device

RAM

EEPROM

ST62T53B

1 x 64 bytes

ST62T60B/E60B

1 x 64 bytes

2 x 64 bytes

ST62T63B

1 x 64 bytes

RAM and EEPROM

000h

03Fh

DATA ROM WINDOW AREA

040h

07Fh

X REGISTER

080h

Y REGISTER

081h

V REGISTER

082h

W REGISTE R

083h

DATA RAM 60 BYTES

084h

0BFh

PORT A DATA REGISTER

0C0h

PORT B DATA REGISTER

0C1h

PORT C DATA REGISTE R

0C2h

RESERVED

0C3h

PORT A DIRECTION REGISTER

0C4h

PORT B DIRECTION REGISTER

0C5h

PORT C DIREC TION REGISTER

0C6h

RESERVED

0C7h

INTERRUPT OPTION REGIS TER

0C8h*

DATA ROM WINDOW REGISTER

0C9h*

RESERVED

0CAh

0CBh

PORT A OPTION REGISTER

0CCh

PORT B OPTION REGISTER

0CDh

PORT C OPTION REGISTER

0CEh

RESERVED

0CFh

A/D DATA REGISTE R

0D0h

A/D CONTROL REGISTER

0D1h

TIMER PRESCA LER REGISTER

0D2h

TIMER COUNTE R REGISTER

0D3h

TIMER STATUS CONTROL REGISTER

0D4h

AR TIMER MODE CONTROL REGISTER

0D5h

AR TIMER STATUS/ CONTROL REGISTER1

0D6h

AR TIMER STATUS/ CONTROL REGISTER2

0D7h

WATCHDO G REGISTER

0D8h

AR TIMER RELOAD/CAPTU RE REGISTER

0D9h

AR TIMER COMPARE REGISTER

0DAh

AR TIMER LOAD REGISTER

0DBh

OSCILLATOR CONTROL REGISTE R

0DCh*

MISCELLANEOUS

0DDh

RESERVED

0DEh

0DFh

SPI DATA REGISTER

0E0h

SPI DIVIDER REGISTER

0E1h

SPI MODE REGISTER

0E2h

RESERVED

0E3h

0E7h

DATA RAM/EEPRO M REGISTER

0E8h*

RESERVED

0E9h

EEPROM CONTROL REGISTER

(except ST62T53B)

0EAh

RESERVED

0EBh

0FEh

ACCUMULATOR

0FFh

* WRITE ONLY REGISTER

10/75

ST62T53B/T60B/T63B ST62E60B

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from

address 0040h to address 007Fh in Data space. It

allows direct reading of 64 consecutive bytes locat-

ed anywhere in program memory, between ad-

dress 0000h and 0FFFh (top memory address de-

pends on the specific device). All the program

memory can therefore be used to store either in-

structions or read-only data. Indeed, the window

can be moved in steps of 64 bytes along the pro-

gram memory by writing the appropriate code in the

Data Window Register (DWR).

The DWR can be addressed like any RAM location

in the Data Space, it is however a write-only regis-

ter and therefore cannot be accessed using single-

bit operations. This register is used to position the

64-byte read-only data window (from address 40h

to address 7Fh of the Data space) in program

memory in 64-byte steps. The effective address of

the byte to be read as data in program memory is

obtained by concatenating the 6 least significant

bits of the register address given in the instruction

(as least significant bits) and the content of the

DWR register (as most significant bits), as illustrat-

ed in Figure 6 below. For instance, when address-

ing location 0040h of the Data Space, with 0 load-

ed in the DWR register, the physical location ad-

dressed in program memory is 00h. The DWR reg-

ister is not cleared on reset, therefore it must be

written to prior to the first access to the Data read-

only memory window area.

Data Window Register (DWR)

Address: 0C9h

—

Write Only

Bits 6, 7 = Not used.

Bit 5-0 = DWR6-DWR0:

Data read-only memory

Window Register Bits. These are the Data read-

only memory Window bits that correspond to the

upper bits of the data read-only memory space.

Caution:

This register is undefined on reset. Nei-

ther read nor single bit instructions may be used to

address this register.

Note: Care is required when handling the DWR

DWR contents should not be changed while exe-

cuting an interrupt service routine, as the service

routine cannot save and then restore the register’s

previous contents. If it is impossible to avoid writ-

ing to the DWR during the interrupt service routine,

an image of the register must be saved in a RAM

location, and each time the program writes to the

DWR, it must also write to the image register. The

image register must be written first so that, if an in-

terrupt occurs between the two instructions, the

DWR is not affected.

Figure 6. Data read-only memory Window Memory Addressing

DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

READ

VR01573C

DATA SPACE ADDRESS

59h

Example:

(DWR)

DWR=28h

ROM

ADDRESS:A19h

11/75

ST62T53B/T60B/T63B ST62E60B

MEMORY MAP (Cont’d)

1.3.6

Data

RAM/EEPROM

Bank

Register

(DRBR)

Address: E8h

—

Write only

Bit 7-5 = These bits are not used

Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2.

Bit 3-2 - Reserved. These bits are not used.

Bit 1 - DRBR1. This bit, when set, selects

EEPROM Page 1.

Bit 0 - DRBR0. This bit, when set, selects

EEPROM Page 0.

The selection of the bank is made by programming

the Data RAM Bank Switch register (DRBR regis-

ter) located at address E8h of the Data Space ac-

cording to Table 1. No more than one bank should

be set at a time.

The DRBR register can be addressed like a RAM

Data Space at the address E8h; nevertheless it is

a write only register that cannot be accessed with

single-bit operations. This register is used to select

the desired 64-byte RAM/EEPROM bank of the

Data Space. The number of banks has to be load-

ed in the DRBR register and the instruction has to

point to the selected location as if it was in bank 0

(from 00h address to 3Fh address).

This register is not cleared during the MCU initiali-

zation, therefore it must be written before the first

access to the Data Space bank region. Refer to

the Data Space description for additional informa-

tion. The DRBR register is not modified when an

interrupt or a subroutine occurs.

Notes :

Care is required when handling the DRBR register

as it is write only. For this reason, it is not allowed

to change the DRBR contents while executing in-

terrupt service routine, as the service routine can-

not save and then restore its previous content. If it

is impossible to avoid the writing of this register in

interrupt service routine, an image of this register

must be saved in a RAM location, and each time

the program writes to DRBR it must write also to

the image register. The image register must be

written first, so if an interrupt occurs between the

two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Other-

wise two or more pages are enabled in parallel,

producing errors.

Table 3. Data RAM Bank Register Set-up

DRBR

DRBR

ST62T53B

ST62T60B/E60B

ST62T63B

None

Not Available

EEPROM Page 0

Not Available

EEPROM Page 1

Not Available

10h

RAM Page 2

other

Reserved

12/75

ST62T53B/T60B/T63B ST62E60B

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in

data space. This memory may be used by the user

program for non-volatile data storage.

Data space from 00h to 3Fh is paged as described

in Table 4. EEPROM locations are accessed di-

rectly by addressing these paged sections of data

space.

The EEPROM does not require dedicated instruc-

tions for read or write access. Once selected via the

Data RAM Bank Register, the active EEPROM

page is controlled by the EEPROM Control Regis-

ter (EECTL), which is described below.

Bit E20FF of the EECTL register must be reset prior

to any write or read access to the EEPROM. If no

bank has been selected, or if E2OFF is set, any ac-

cess is meaningless.

Programming must be enabled by setting the

E2ENA bit of the EECTL register.

The E2BUSY bit of the EECTL register is set when

the EEPROM is performing a programming cycle.

Any access to the EEPROM when E2BUSY is set

is meaningless.

Provided E2OFF and E2BUSY are reset, an EEP-

ROM location is read just like any other data loca-

tion, also in terms of access time.

Writing to the EEPROM may be carried out in two

modes: Byte Mode (BMODE) and Parallel Mode

(PMODE). In BMODE, one byte is accessed at a

time, while in PMODE up to 8 bytes in the same

row are programmed simultaneously (with conse-

quent speed and power consumption advantages,

the latter being particularly important in battery

powered circuits).

General Notes:

Data should be written directly to the intended ad-

dress in EEPROM space. There is no buffer mem-

ory between data RAM and the EEPROM space.

When the EEPROM is busy (E2BUSY = “1”)

EECTL cannot be accessed in write mode, it is

only possible to read the status of E2BUSY. This

implies that as long as the EEPROM is busy, it is

not possible to change the status of the EEPROM

Control Register. EECTL bits 4 and 5 are reserved

and must never be set.

Care is required when dealing with the EECTL reg-

ister, as some bits are write only. For this reason,

the EECTL contents must not be altered while ex-

ecuting an interrupt service routine.

If it is impossible to avoid writing to this register

within an interrupt service routine, an image of the

each time the program writes to EECTL it must

also write to the image register. The image register

must be written to first so that, if an interrupt oc-

curs between the two instructions, the EECTL will

not be affected.

Table 4. . Row Arrangement for Parallel Writing of EEPROM Locations

Dataspace

addresses.

Banks 0 and 1.

Byte

ROW7

38h-3Fh

ROW6

30h-37h

ROW5

28h-2Fh

ROW4

20h-27h

ROW3

18h-1Fh

ROW2

10h-17h

ROW1