COP87L88EK/RK Family 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory, Comparator, and Single-slope A/D Capability

COP87L88EK/RK Family

8-Bit CMOS OTP Microcontrollers with 8k or 32k

Memory, Comparator, and Single-slope A/D Capability

General Description

The COP87L88EK/RK Family OTP (One Time Program-

mable) microcontrollers are highly integrated COP8

™

Fea-

ture core devices with 16k or 32k memory and advanced

features

including

Multi-Input

Comparator

and

Single-slope A/D capability. These multi-chip CMOS devices

are suited for applications requiring a full featured, low EMI

controller with an analog comparator, current source, and

voltage reference, and as pre-production devices for a

masked ROM design. Lower cost pin and software compat-

ible 8k ROM versions (COP888EK) are available for use with

a range of COP8 software and hardware development tools.

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI (-XE = crystal oscillator) with 1 µs instruc-

tion cycle, three multi-function 16-bit timer/counters with

PWM, MICROWIRE/PLUS

™

serial I/O, one analog com-

parator with seven input multiplexor, an analog current

source and V

/2 reference, two power saving HALT/IDLE

modes, idle timer, MIWU, high current outputs, software se-

lectable I/O options, WATCHDOG

™

timer and Clock Monitor,

2.7V to 5.5V operation and 28/40/44 pin packages.

Devices included in this datasheet are:

Device

Memory (bytes)

RAM (bytes)

I/O Pins

Packages

Temperature

COP87L84EK

16k OTP EPROM

256

28 DIP/SOIC

-40 to +85˚C

COP87L88EK

16k OTP EPROM

256

36/40

40 DIP, 44 PLCC

-40 to +85˚C

COP87L84RK

32k OTP EPROM

256

28 DIP/SOIC

-40 to +85˚C

COP87L88RK

32k OTP EPROM

256

36/40

40 DIP, 44 PLCC

-40 to +85˚C

Key Features

Analog function block with

— Analog comparator with seven input multiplexor

— Constant current source and V

/2 reference

Three 16-bit timers, each with two 16-bit registers

supporting:

— Processor Independent PWM mode

— External Event counter mode

— Input Capture mode

8 or 32 kbytes on-board EPROM with security feature

256 bytes on-board RAM

Additional Peripheral Features

Idle Timer

Multi-Input Wake Up (MIWU) with optional interrupts (8)

WATCHDOG and Clock Monitor logic

MICROWIRE/PLUS serial I/O

I/O Features

Software selectable I/O options ( TRI-STATE

™

Output,

Push-Pull Output, Weak Pull-Up Input, High Impedance

Input)

Packages:

— 44 PLCC with 40 I/O pins

— 40 DIP with 36 I/O pins

— 28 DIP/SO with 24 I/O pins

Schmitt trigger inputs on Port G and L

CPU/Instruction Set Feature

1 µs instruction cycle time

Twelve multi-source vectored interrupts servicing

— External Interrupt with selectable edge

— Idle Timer T0

— Three Timers (Each with 2 interrupts)

— MICROWIRE/PLUS

— Multi-Input Wake Up

— Software Trap

— Default VIS (default interrupt)

Versatile and easy to use instruction set

8-bit Stack Pointer (SP) — stack in RAM

Two 8-bit Register Indirect Data Memory Pointers

(B, X)

Fully Static CMOS

Two power saving modes: HALT and IDLE

Single supply operation: 2.7V to 5.5V

Temperature ranges: −40˚C to +85˚C

Development Support

Emulation devices for the COP888EK/COP884EK

Real time emulation and full program debug offered by

MetaLink Development System

COP8

™

is a trademark of National Semiconductor Corporation.

MICROWIRE/PLUS

™

is a trademark of National Semiconductor Corporation.

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

WATCHDOG

™

is a trademark of National Semiconductor Corporation.

iceMASTER

™

is a trademark of MetaLink Corporation.

September 1999

COP87L88EK/RK

Family,

8-Bit

CMOS

OTP

Microcontrollers

with

32k

Memory

Comparator

and

Single-slope

A/D

Capability

DS101133

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Connection Diagrams

(Continued)

Pinouts for 28-, 40-, and 44-Pin Packages

Port

Type

Alt. Fun

28-Pin

40-Pin

44-Pin

Pack.

I/O

MIWU

I/O

MIWU

I/O

MIWU

I/O

MIWU

I/O

MIWU

T2A

I/O

MIWU

T2B

I/O

MIWU

T3A

I/O

MIWU

T3B

I/O

INT

WDOUT

I/O

T1B

I/O

T1A

I/O

I/CKO

HALT Restart

COMPIN1+

COMPIN−/Current

Source Out

COMPIN0+

COMPOUT/COMPIN2+

COMPIN3+

COMPIN4+

COMPIN5+

COMPOUT

I/O

GND

CKI

RESET

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Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)

Voltage at Any Pin

−0.3V to V

+ 0.3V

Total Current into V

Pin (Source)

100 mA

Total Current out of GND Pin (Sink)

110 mA

Storage Temperature Range

−65˚C to +140˚C

Note 1:

Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

DC Electrical Characteristics

−40˚C

≤

+85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Operating Voltage

2.7

5.5

Power Supply Ripple (Note 3)

Peak-to-Peak

0.1 V

Supply Current (Note 4)

CKI = 10 MHz

= 5.5V, t

= 1 µs

16.5

CKI = 4 MHz

= 4.0V, t

= 2.5 µs

6.5

HALT Current (Note 5)

= 5.5V, CKI = 0 MHz

µA

= 4.0V, CKI = 0 MHz

µA

IDLE Current (Note 4)

CKI = 10 MHz

= 5.5V, t

= 1 µs

3.5

CKI = 4 MHz

= 4.0V, t

= 10 µs

0.7

Input Levels (V

, V

)

RESET

Logic High

0.8 V

Logic Low

0.2 V

CKI, All Other Inputs

Logic High

0.7 V

Logic Low

0.2 V

Hi-Z Input Leakage

= 5.5V

−2

µA

Input Pullup Current

= 5.5V, V

= 0V

−40

−250

µA

G and L Port Input Hysteresis (Note 8)

0.35 V

Output Current Levels

D Outputs

Source

= 4.5V, V

= 3.3V

−0.4

Sink

= 4.5V, V

= 1V

All Others

Source (Weak Pull-Up Mode)

= 4.5V, V

= 2.7V

−10

−110

µA

Source (Push-Pull Mode)

= 4.5V, V

= 3.3V

−0.4

Sink (Push-Pull Mode)

= 4.5V, V

= 0.4V

1.6

TRI-STATE Leakage

= 6.0V

−2

µA

Allowable Sink/Source Current per Pin

(Note 8)

D Outputs (Sink)

All others

Maximum Input Current

Room Temp

200

without Latchup (Note 6)

RAM Retention Voltage, V

500 ns Rise

and Fall Time (min)

Input Capacitance

Load Capacitance on D2

1000

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AC Electrical Characteristics

−40˚C

≤

+85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

)

Crystal, Resonator,

4.5V

≤

5.5V

1.0

µs

R/C Oscillator

4.5V

≤

5.5V

3.0

µs

Inputs

SETUP

4.5V

≤

5.5V

200

HOLD

4.5V

≤

5.5V

Output Propagation Delay (Note 7)

= 2.2k, C

= 100 pF

PD1

, t

PD0

SO, SK

4.5V

≤

5.5V

0.7

µs

All Others

4.50V

≤

5.5V

1.0

µs

MICROWIRE Setup Time (t

UWS

) (Note 7)

≥

4.5V

MICROWIRE Hold Time (t

UWH

) (Note 7)

≥

4.5V

MICROWIRE Output Propagation Delay (t

UPD

)

≥

4.5V

220

Input Pulse Width (Note 8)

Interrupt Input High Time

1.0

Interrupt Input Low Time

1.0

Timer 1, 2, 3 Input High Time

1.0

Timer 1, 2, 3 Input Low Time

1.0

Reset Pulse Width

1.0

µs

Note 2: t

= Instruction Cycle Time

Note 3: Maximum rate of voltage change must be

0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V

and outputs driven low but not connected to a load.

Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I

HALT is done with device neither sourcing nor

sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to

; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT

in crystal clock mode.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages

and the pins will have sink current to V

when

biased at voltages

(the pins do not have source current when biased at a voltage below V

). The effective resistance to V

is 750

Ω

(typical). These two

pins will not latch up. The voltage at the pins must be limited to

14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-

cludes ESD transients.

Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 8: Parameter characterized but not tested.

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Analog Function Block AC and DC Characteristics

= 5.0V, −40˚C

≤

+85˚C

Parameter

Conditions

Min

Typ

Max

Units

Input Offset Voltage

0.4V

− 1.5V

Input Common Mode Voltage Range

(Note 10)

0.4

− 1.5

/2 Reference

4.5V

5.5V

0.5 V

− 0.04

0.5 V

+ 0.04

DC Supply Current for

= 5.5V

250

µA

Comparator (when enabled)

DC Supply Current for

= 5.5V

µA

/2 Reference (when enabled)

DC Supply Current for

= 5.5V

200

µA

Constant Current Source (when enabled)

Constant Current Source

4.5V

5.5V

µA

Current Source Variation over

4.5V

5.5V

µA

Common Mode Range

Temp = Constant

Current Source Enable Time

1.5

µs

Comparator Response Time

100 mV Overdrive,

µs

100 pF Load

Note 9: While performance characteristics are given at V

= 5.0V, the analog function block will operate over the entire 2.5V–6.0V V

range. Accuracy of the

/2 reference and the constant current source is not guaranteed beyond the specified limits.

Note 10: The device is capable of operating over a common mode voltage range of 0 to V

− 1.5V, however increased offset voltage will be observed between 0V

and 0.4V.

Typical Performance Characteristics

(−55˚C

≤

= +125˚C)

DS101133-18

FIGURE 3. MICROWIRE/PLUS Timing

DS101133-19

DS101133-20

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Typical Performance Characteristics

(−55˚C

≤

= +125˚C) (Continued)

Pin Descriptions

and GND are the power supply pins. All V

and GND

pins must be connected.

CKI is the clock input. This can come from an R/C generated

oscillator, or a crystal oscillator (in conjunction with CKO).

See Oscillator Description section.

RESET is the master reset input. See Reset Description sec-

tion.

The device contains three bidirectional 8-bit I/O ports (C, G

and L), where each individual bit may be independently con-

figured as an input (Schmitt Trigger inputs on ports L and G),

output or TRI-STATE under program control. Three data

memory address locations are allocated for each of these

I/O ports. Each I/O port has two associated 8-bit memory

mapped registers, the CONFIGURATION register and the

output DATA register. A memory mapped address is also re-

served for the input pins of each I/O port. (See the memory

map for the various addresses associated with the I/O ports.)

Figure 4 shows the I/O port configurations. The DATA and

CONFIGURATION registers allow for each port bit to be in-

dividually configured under software control as shown below:

CONFIGURA-

TION

DATA

Port Set-Up

Register

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers

on the inputs.

The Port L supports Multi-Input Wake Up on all eight pins. L4

and L5 are used for the timer input functions T2A and T2B.

L6 and L7 are used for the timer input functions T3A and

T3B.

The Port L has the following alternate features:

MIWU or T3B

MIWU or T3A

MIWU or T2B

MIWU or T2A

MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input

pin (G6), and a dedicated output pin (G7). Pins G0 and

G2–G6 all have Schmitt Triggers on their inputs. Pin G1

serves as the dedicated WDOUT WATCHDOG output, while

pin G7 is either input or output depending on the oscillator

mask option selected. With the crystal oscillator option se-

lected, G7 serves as the dedicated output pin for the CKO

clock output. With the single-pin R/C oscillator mask option

selected, G7 serves as a general purpose input pin but is

also used to bring the device out of HALT mode with a low to

high transition on G7. There are two registers associated

with the G Port, a data register and a configuration register.

Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-

vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose in-

put (R/C clock option), the associated bits in the data and

configuration registers for G6 and G7 are used for special

purpose functions as outlined on the next page. Reading the

G6 and G7 data bits will return zeros.

DS101133-30

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Pin Descriptions

(Continued)

Note that the chip will be placed in the HALT mode by writing

a “1” to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredicatable values.

PORT I is an eight-bit Hi-Z input port. The 28-pin device does

not have a full complement of Port I pins. The unavailable

pins are not terminated i.e., they are floating. A read opera-

tion for these unterminated pins will return unpredictable val-

ues. The user must ensure that the software takes this into

account by either masking or restricting the accesses to bit

operations. The unterminated Port I pins will draw power

only when addressed.

Port I is an eight-bit Hi-Z input port.

Port I0–I7 are used for the analog function block.

The Port I has the following alternate features:

COMPOUT (Comparator Output)

COMPIN5+ (Comparator Positive Input 5)

COMPIN4+ (Comparator Positive Input 4)

COMPIN3+ (Comparator Positive Input 3)

COMPOUT/COMPIN2+

(Comparator

Output/

Comparator Positive Input 2))

COMPIN0+ (Comparator Positive Input 0)

COMPIN−

(Comparator

Negative

Input/Current

Source Out)

COMPIN1+ (Comparator Positive Input 1)

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

above 0.8 V

to prevent the chip from entering special modes. Also

keep the external loading on D2 to

1000 pF.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally