MULTISYNC ON-SCREEN DISPLAY FOR MONITOR

STV9420

STV9421

October 1995

DIP20

(Plastic Package)

ORDER CODE : STV9421

CMOS SINGLE CHIP OSD FOR MONITOR

BUILT IN 1 KBYTE RAM HOLDING :

- PAGES’ DESCRIPTORS

- CHARACTER CODES

- USER DEFINABLE CHARACTERS

128 ALPHANUMERIC CHARACTERS OR

GRAPHIC SYMBOLS IN INTERNAL ROM

(12 x 18 DOT MATRIX)

UP TO 26 USER DEFINABLE CHARACTERS

INTERNAL HORIZONTAL PLL (15 TO 120kHz)

PROGRAMMABLE VERTICAL HEIGHT OF

CHARACTER WITH A SLICE INTERPOLATOR

TO MEET MULTI-SYNCH REQUIREMENTS

PROGRAMMABLE VERTICAL AND HORI-

ZONTAL POSITIONING

FLEXIBLE SCREEN DESCRIPTION

CHARACTER BY CHARACTER COLOR SE-

LECTION (UP TO 8 DIFFERENT COLORS)

PROGRAMMABLE BACKGROUND (COLOR,

TRANSPARENT OR WITH SHADOWING)

CHARACTER BLINKING

2-WIRES ASYNCHRONOUS SERIAL MCU

INTERFACE (I

C PROTOCOL)

4 x 8 BITS PWM DAC OUTPUTS ON THE

STV9421

SINGLE POSITIVE 5V SUPPLY

DIP16

(Plastic Package)

ORDER CODE : STV9420

DESCRIPTION

The STV9420/21 is an ON SCREEN DISPLAY for

monitor. It is built as a slave peripheral connected

to a host MCU via a serial I

C bus. It includes a

display memory, controls all the display attributes

and generates pixels from the data read in its on

chip memory. The line PLL and a special slice

interpolator allow to have a display aspect which

does not depend on the line and frame frequencies.

C interface allows MCU to make transparent in-

ternal access to prepare the next pages during the

display of the current page. Toggle from one page

to another by programming only one register.

4 x 8 bits PWM DAC are available (STV9421) to

provide DC voltage control to other peripherals.

The STV9420/21 provides the user an easy to use

and cost effective solution to display alphanumeric

or graphic information on monitor screen.

1/16

9420-01.AI

9421-01.AI

PIN CONNECTIONS

PIN DESCRIPTION

Symbol

Pin Number

I/O

Description

DIP16

DIP20

PWM1

DAC1 Output

FBLK

Fast Blanking Output

H-SYNC

Horizontal Sync Input

V-SYNC

Vertical Sync Input

+5V Supply

PXCK

Pixel Frequency Output

CKOUT

Clock Output

XTALOUT

Crystal Output

XTALIN

Crystal or Clock Input

PWM4

DAC4 Output

PWM2

DAC2 Output

SCL

Serial Clock

SDA

I/O

Serial Input/output Data

RESET

Reset Input

GND

Ground

Red Output

Green Output

Blue Output

TEST

Reserved (grounded in Normal Operation)

PWM3

DAC3 Output

9420-01.TBL

TEST

GND

RESET

SDA

SCL

FBLK

H-SYNC

V-SYNC

PXCK

CKOUT

XTALOUT

XTALIN

DIP16

PWM3

TEST

GND

RESET

SDA

SCL

PWM2

PWM1

FBLK

H-SYNC

V-SYNC

PXCK

CKOUT

XTALOUT

XTALIN

PWM4

DIP20

STV9420 - STV9421

2/16

1 0

1 2

1 3

1 6

CKOUT

HS YNC

VSYNC

RESE T

FBLK

GND

S CL

S DA

XTAL

OUT

PXCK

TES T

Addre ss /Da ta

S TV9420

HORIZONTAL

DIGITAL P LL

4K ROM

(128 cha ra cte rs )

1K RAM

P ag e De s criptors +

Us e r De fine d C ha r.

I C BUS

INTERFACE

DISPLAY

CONTROLLER

9420-02.EPS

BLOCK DIAGRAMS

STV9420

PWM

P WM3

P WM2

P WM1

P WM4

CKOUT

HS YNC

VSYNC

RES E T

FBLK

GND

S CL

S DA

XTAL

OUT

P XCK

TES T

Addres s /Data

S TV9421

DISP LAY

CONTROLLER

HORIZONTAL

DIGITAL P LL

4K ROM

(128 cha racte rs )

I C BUS

INTERFACE

1K RAM

P a ge Des criptors +

Use r Define d Cha r.

9421-02.EPS

STV9421

STV9420 - STV9421

3/16

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

Supply Voltage

-0.3, +7.0

Input Voltage

-0.3, +7.0

oper

Operating Ambient Temperature

0, +70

stg

Storage Temperature

-40, +125

9420-02.TBL

ELECTRICAL CHARACTERISTICS

= 5V, V

= 0V, T

= 0 to 70

C, F

XTAL

= 8 to 15MHz, TEST = 0 V, unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

SUPPLY

Supply Voltage

4.75

5.25

Supply Current

INPUTS

SCL, SDA, TEST, RESET, V-SYNC and H-SYNC

Input Low Voltage

0.8

Input High Voltage

0.8 V

Input Leakage Current

-20

+20

OUTPUTS

R, G, B, FBLK, SDA, CKOUT, PXCK and PWMi (i = 1 to 4)

Output Low Voltage (I

= 1.6mA)

0.4

Output High Voltage (I

= -0.1mA)

0.8 V

9420-03.TBL

For R, G, B and FBLK outputs, see Figure 1.

2.5

-5

-4

-3

-2

-1

I (A)

(V)

9420-17.EPS

Figure 1 : Typical R, G, B Outputs Characteristics

STV9420 - STV9421

4/16

TIMINGS

Symbol

Parameter

Min.

Typ.

Max.

Unit

OSCILATOR INPUT : XTI (see Figure 2)

Clock High Level

Clock Low Level

XTAL

Clock Frequency

MHz

PXL

Pixel Frequency

MHz

RESET

RES

Reset High Level Pulse

R, G, B, FBLK (C

LOAD

= 30pF)

Rise Time (Note 1)

Fall Time (Note 1)

SKEW

Skew between R, G, B, FBLK (Note 1)

C INTERFACE : SDA AND SCL (see Figure 3)

SCL

SCL Clock Frequency

MHz

BUF

Time the bus must be free between 2 access

500

HDS

Hold Time for Start Condition

500

SUP

Set up Time for Stop Condition

500

LOW

The Low Period of Clock

400

HIGH

The High Period of Clock

400

HDAT

Hold Time Data

SUDAT

Set up Time Data

375

Fall Time of SDA

Rise Time of Both SCL and SDA

Depend on the pull-up resistor

and the load capacitance

Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes

characterization on batches comming from corners of our processes and also temperature characterization.

9420-04.TBL

XTI

W H

9420-03.EPS

Figure 2

S DA

BUF

S CL

HDAT

S T OP

S TART

DATA

S TOP

S UDAT

HDS

S UP

HIGH

LOW

9420-04.EPS

Figure 3

STV9420 - STV9421

5/16

FUNCTIONAL DESCRIPTION

The STV9420/21 display processor operation is

controlled by a host MCU via the I

C interface. It is

fully programmable through 8 internal read/write

registers (12 for STV9421) and performs all the

display functions by generating pixels from data

stored in its internal memory. After the page down-

loading from the MCU, the STV9420/21 refreshes

screen by its built in processor, without any MCU

control (access).In addition, the host MCU has a

direct access to the on chip 1Kbytes RAM during

the display of the current page to make any update

of its contents.

With the STV9420/21, a page displayed on the

screen is made of several strips which can be of 2

types : spacing or character and which are de-

scribed by a table of descriptors and character

codes in RAM. Several pages can be downloaded

at the same time in the RAM and the choice of the

current display page is made by programming the

CONTROL register.

I - Serial Interface

The 2-wires serial interface is an I

C interface. To

be connected to the I

C bus, a device must own its

sl ave ad dr ess ; the sla ve address of t he

STV9420/21 is BA (in hexadecimal).

R/W

I.1 - Data Transfer in Write Mode

The host MCU can write data into the STV9420/21

registers or RAM.

To write data into the STV9420/21, after a start, the

MCU must send (Figure 3) :

- First, the I

C address slave byte with a low level

for the R/W bit,

- The two bytes of the internal address where the

MCU wants to write data(s),

- The successive bytes of data(s).

All bytes are sent MS bit first and the write data

transfer is closed by a stop.

I.2 - Data Transfer in Read Mode

The host MCU can read data from the STV9420/21

registers, RAM or ROM.

To read data from the STV9420/21 (Figure 4), the

MCU must send 2 different I

C sequences.

The first one is made of I

C slave address byte with

R/W bit at low level and the 2 internal address

bytes.

The second one is made of I

C slave address byte

with R/W bit at high level and all the successive

data bytes read at successive addresses starting

from the initial address given by the first sequence.

SCL

SDA

R/W

C Slave Address

ACK

LSB Address

ACK

MSB Address

ACK

Start

A13 A12 A10 A10 A9

Stop

SCL

SDA

R/W

C Slave Address

ACK

Data Byte n

ACK

Start

Stop

Data Byte 1

9420-06.EPS

Figure 4 : STV9420/I

C Read Operation

SCL

SDA

R/W

A13

A12

A11

A10

C Slave Address

ACK

LSB Address

ACK

MSB Address

ACK

Start

ACK

Data Byte 1

Data Byte 2

ACK

Data Byte n

Stop

SCL

SDA

9420-05.AI

Figure 3 : STV9420/I

C Write Operation

STV9420 - STV9421

6/16

FUNCTIONAL DESCRIPTION (continued)

I.3 - Addressing Space

STV9420/21registers, RAM and ROM are mapped

in a 16Kbytes addressing space. The mapping is

the following :

0000

Descriptors character

codes user definable

characters

1024 bytes

RAM

03FF

0400

Empty

Space

1FFF

2000

Character

Generator

ROM

32FF

3300

Empty

Space

3FFF

3FF0

Internal

Registers

3FFF

I.4 - Register Set

LINE DURATION

3FF0

LD5

LD4

LD3

LD2

LD1

LD0

LD[5:0] : LINE DURATION (number of character

period, 1LSB = 12 pixel periods).

HORIZONTAL DELAY

3FF1

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

DD[7:0] : HORIZONTAL DISPLAY DELAY from

the H-SYNC reference falling edge to

the 1

pixel position of the character

strips.

Unit = 3 pixel periods.

CHARACTERS HEIGHT

3FF2

CH5 CH4 CH3 CH2 CH1 CH0

CH[5:0] : HEIGHT of the character strips in scan

lines. For each scan line, the number of

the slice which is displayed is given by :

S LI CE -NU MBER

round







SCAN

LINE

NUMBER x 18

CH[5:0]







SCAN-LINE-NUMBER = Number of the current scan

line of the strip.

DISPLAY CONTROL

3FF3

OSD FBK

FL1

FL0

OSD

: ON/OFF (if 0, R, G, B and FBLK are 0).

FBK

: Fast blanking control :

= 1 : FBLK = 1, forcing black where

these is no display,

= 0 : FBLK is active only during

character display.

FL[1:0] : Flashing mode :

- 00 : No flashing. The character

attribute is ignored,

- 01 : 1/1 flashing (a duty cycle = 50%),

- 10 : 1/3 flashing,

- 11 : 3/1 flashing.

P[8:6]

: Address of the 1

descriptor of the

current displayed pages.

P[13:9] and P[5:0] = 0 ; up to 8 different

pages can be stored in the RAM.

LOCKING CONDITION TIME CONSTANT

3FF4

AS2 AS1 AS0

BS2 BS1 BS0

: Free Running ; if = 1 PLL is disabled and

the pixel frequency keeps its last value.

AS[2:0] : Ph a s e co n st a n t d ur i n g l o c ki n g

conditions.

BS[2:0] : Frequency constant during locking

conditions.

CAPTURE PROCESS TIME CONSTANT

3FF5

AF2

AF1

AF0

BF2

BF1

BF0

AF[2:0] : Phase constant during the capture

process.

BF[2:0] : Frequency constant during the capture

process.

INITIAL PIXEL PERIOD

3FF6

PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0

PP[7:0] : Value to initialize the pixel period of the

PLL.

FREQUENCY MULTIPLIER

3FF7

FM3 FM2 FM1 FM0

FM[3:0] : Frequency multiplier of the crystal

frequency to reach the high frequency

used by the PLL to derive the pixel

frequency.

STV9420 - STV9421

7/16

FUNCTIONAL DESCRIPTION (continued)

The last fourth registers described below are only

available with the STV9421 :

PULSE WIDTH MODULATOR 1

3FF8

V17

V16

V15

V14

V13

V12

V11

V10

V1[7:0] : Digital value of the 1

PWM D to A

converter (Pin1).

PULSE WIDTH MODULATOR 2

3FF9

V27

V26

V25

V24

V23

V22

V21

V20

V2[7:0] : Digital value of the 2

PWM DAC (Pin11).

PULSE WIDTH MODULATOR 3

3FFA

V37

V36

V35

V34

V33

V32

V31

V30

V3[7:0] : Digital value of the 3

PWM DAC

(Pin20).

PULSE WIDTH MODULATOR 4

3FFB

V47

V46

V45

V44

V43

V42

V41

V40

V4[7:0] : Digital value of the 4

PWM DAC

(Pin10).

Note : * is power on reset value.

II - Descriptors

SPACING

MSB

LSB

SL7

SL6

SL5

SL4

SL3

SL2

SL1

SL0

SL[7:0] : The number of the scan lines of the

spacing strip (1 to 255).

CHARACTER

MSB

LSB

C[9:0] : The address of the first character code of

the strip (even).

: Display enable :

- DE = 0, R = G = B = 0 and FBLK = FBK

(display control register) on whole strip,

- DE = 1, display of the characters.

: Zoom, ZY = 1 all the scan lines are

repeated once.

III - Code Format

MSB

SET

CHARACTER NUMBER

LSB

BK3 BK2 BK1 BK0

FL : Flashing attribute (the flashing mode is

defined in the DISPLAY CONTROL register).