radpal1.PDF

Standard Products

UT22VP10 Universal RAD

PAL

Data Sheet

November 2000

FEATURES

q High speed Universal RAD

PAL

- tPD: 15.5ns, 20ns, 25ns maximum

- fMAX1: 33MHz maximum external frequency

- Supported by industry-standard programmer

- Amorphous silicon anti-fuse

q Asynchronous and synchronous RAD

PAL

operation

- Synchronous PRESET

- Asynchronous RESET

q Up to 22 input and 10 output drivers may be configured

- CMOS & TTL-compatible input and output levels

- Three-state output drivers

q Variable product terms, 8 to 16 per output

q 10 user-programmable output macrocells

- Registered or combinatorial operation

- Output driver polarity control selectable

- Two feedback paths available

q Radiation-hardened process and design; total dose irradia-

tion testing to MIL-STD-883, Method 1019

- Total dose: 1.0E6 rads(Si)

- Upset threshold 50 MeV-cm

/mg (min)

- Latchup immune(LET>109 MeV-cm

/mg)

q QML Q & V compliant

q Packaging options:

- 24-pin 100-mil center DIP (0.300 x 1.2)

- 24-lead flatpack (.45 x .64)

- 28-lead quad-flatpack (.45 x .45)

q Standard Military Drawing 5962-94754 available

Macrocell

Reset

Preset

Figure 1. Block Diagram

PROGRAMMABLE ARRAY LOGIC

(132 X 44)

PRODUCT DESCRIPTION

The UT22VP10 RAD

PAL

is a fuse programmable logic array

device. The familiar sum-of-products (AND-OR) logic struc-

ture is complemented with a programmable macrocell. The

UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and

28-lead quad-flatpack package offerings providing up to 22

inputs and 10 outputs. Amorphous silicon anti-fuse technology

provides the programming of each output. The user specifies

whether each of the potential outputs is registered or combina-

torial. Output polarity is also individually selected, allowing for

greater flexibility for output configuration. A unique output en-

able function allows the user to configure bidirectional I/O on

an individual basis.

The UT22VP10 architecture implements variable sum terms

providing 8 to 16 product terms to outputs. This feature provides

the user with increased logic function flexibility. Other features

include common synchronous preset and asynchronous reset.

These features eliminate the need for performing the initializa-

tion function.

The UT22VP10 provides a device with the flexibility to imple-

ment logic functions in the 500 to 800 gate complexity. The

flexible architecture supports the implementation of logic func-

tions requiring up to 21 inputs and only a single output or down

to 12 inputs and 10 outputs. Development and programming

support for the UT22VP10 is provided by DATA I/O.

DIP & FLATPACK PIN CONFIGURATION

QUAD-FLATPACK PIN CONFIGURATION

PIN NAMES

FUNCTION DESCRIPTION

The UT22VP10 RAD

PAL

implements logic functions as sum-

of-products expressions in a one-time programmable-AND/

fixed-OR logic array. User-defined functions are created by

programming the connections of input signals into the array.

User-configurable output structures in the form of I/O macro-

cells further increase logic flexibility.

CK/I

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

CK/I

Clock/Data Input

Data Input

I/O

Data Input/Output

Power

Ground

I/O2

I/O3

I/O4

I/O5

I/O7

I/O6

CK/I

I/O0 I/O1

I/O9 I/O8

Table 1. Macrocell Configuration Table

1, 2, 3

OVERVIEW

The UT22VP10 RAD

PAL

architecture (see figure 1) has 12 ded-

icated inputs and 10 I/Os to provide up to 22 inputs and 10

outputs for creating logic functions. At the core of the device

is a one-time programmable anti-fuse AND array that drives a

fixed OR array. With this structure, the UT22VP10 can imple-

ment up to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is a macrocell

which is independently programmed to one of six different con-

figurations. The one-time programmable macro cells allow

each I/O to create sequential or combinatorial logic functions

with either Active-High or Active-Low polarity.

LOGIC ARRAY

The one-time programmable AND array of the UT22VP10

RAD

PAL

is formed by input lines intersecting product terms.

The input lines and product terms are used as follows:

44 input lines:

• 24 input lines carry the true and complement of the signals

applied to the input pins

• 20 lines carry the true and complement values of feedback

or input signals from the 10 I/Os

132 product terms:

• 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and

16) used to form logic sums

• 10 output enable terms (one for each I/O)

• 1 global synchronous preset term

• 1 global asynchronous reset term

At each input-line/product-term intersection there is an anti-

fuse cell which determines whether or not there is a logical

connection at that intersection. A product term which is con-

nected to both the true and complement of an input signal will

always be logical zero, and thus will not effect the OR function

that it drives. When there are no connections on a product term

a Don’t Care state exists and that term will always be a logical

one.

PRODUCT TERMS

The UT22VP10 provides 120 product terms that drive the 10

OR functions. The 120 product terms connect to the outputs in

two groups of 8, 10, 12, 14, and 16 to form logical sums.

MACROCELL ARCHITECTURE

The output macrocell provides complete control over the archi-

tecture of each output. Configuring each output independently

permits users to tailor the configuration of the UT22VP10 to

meet design requirements.

Each I/O macrocell (see figure 2) consists of a D flip-flop and

two signal-select multiplexers. Three configuration select bits

controlling the multiplexers determine the configuration of

each UT22VP10 macrocell (see table 1). The configuration se-

lect bits determine output polarity, output type (registered or

combinatorial) and input feedback type (registered or I/O). See

figure 3 for equivalent circuits for the macrocell configurations.

OUTPUT FUNCTIONS

The signal from the OR array may be fed directly to the output

pin (combinatorial function) or latched in the D flip-flop (reg-

istered function). The D flip-flop latches data on the rising edge

of the clock. When the synchronous preset term is satisfied, the

Q output of the D flip-flop output will be set logical one at the

next rising edge of the clock input. Satisfying the asynchronous

clear term sets Q logical zero, regardless of the clock state. If

both terms are satisfied simultaneously, the clear will override

the preset.

Output Type

Polarity

Feedback

Registered

Active LOW

Registered

Active HIGH

Registered

Combinatorial

Active LOW

I/O

Combinatorial

Active HIGH

I/O

Registered

Active LOW

I/O

Registered

Active HIGH

I/O

Notes:

1. 0 equals programmed low or programmed.

2. 1 equals programmed high or unprogrammed.

3. X equals don’t care.

OUTPUT POLARITY

Each macrocell can be configured to implement Active-High

or Active-Low logic. Programmable polarity eliminates the

need for external inverters.

OUTPUT ENABLE

The output of each I/O macrocell can be enabled or disabled

under the control a programmable output enable product term.

The output signal is propagated to the I/O pin when the logical

conditions programmed on the output enable term are satisfied.

Otherwise, the output buffer is driven to the high-impedance

state.

The output enable term allows the I/O pin to function as a ded-

icated input, dedicated output, or bidirectional I/O. When every

connection is unprogrammed, the output enable product term

permanently enables the output buffer and yields a dedicated

output. If every connection is programmed, the enable term is

logically low and the I/O functions as a dedicated input.

REGISTER FEEDBACK

The feedback signal to the AND array is taken from the Q output

when the I/O macrocell implements a registered function

= 0, C

= 0).

BIDIRECTIONAL I/O

The feedback signal is taken from the I/O pin when the macro-

cell implements a combinatorial function (C

= 1) or a regis-

tered function (C

= 1, C

= 0). In this case, the pin can be used

as a dedicated input, a dedicated output, or a bidirectional I/O.

POWER-ON RESET

To ease system initialization, all D flip-flops will power-up to

a reset condition and the Q output will be low. The actual output

of the UT22VP10 will depend on the programmed output po-

larity. The reset delay time is 5

s maximum. See the Power-up

Reset section for a more descriptive list of POR requirements.

ANTI-FUSE SECURITY

The UT22VP10 provides a security bit that prevents unautho-

rized reading or copying of designs programmed into the de-

vice. The security bit is set by the PLD programmer at the con-

clusion of the programming cycle. Once the security bit is set

it is no longer possible to verify (read) or program the

UT22VP10. NOTE: UTMC does not recommend using the

UT22VP10 unless the security fuse has been programmed.

The security bit must be blown to ensure proper function-

ality of the UT22VP10.

OUTPUT

SELECT

MUX

INPUT/

FEEDBACK

MUX

Figure 2. Macrocell

ABSOLUTE MAXIMUM RATINGS

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the

device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2. Minimum voltage is -0.6V

which may undershoot to -2.0V

for pulses of less than 20ns. Maximum output pin voltage is V

+0.75V

which may

overshoot to +7.0V

for pulses of less than 20ns.

3. (I

max + I

) 5.5V.

RECOMMENDED OPERATING CONDITIONS

Notes:

1. See page 12 for minimum V

requirements at power-up.

SYMBOL

PARAMETER

LIMIT

UNITS

Supply voltage

-0.3 to 7.0

I/O

Input voltage any pin

-0.3 to +7.0

STG

Storage Temperature range

-65 to +150

Maximum junction temperature

+175

Lead temperature (soldering 10 seconds)

+300

Thermal resistance junction to case

C/W

DC input current

±10

Maximum power dissipation

1.6

Output sink current

SYMBOL

PARAMETER

LIMIT

UNITS

Supply voltage

4.5 to 5.5

Input voltage any pin

0 to V

Temperature range

-55 to + 125

DC ELECTRICAL CHARACTERISTICS

1, 7

= 5.0V

10%; V

= 0V

-55

°°

C < T

< +125

°°

Notes:

1. All specifications valid for radiation dose < 1E6 rads(Si).

2. See page 12 for minimum V

requirements at power-up.

3. Maximum allowable relative shift equals 50mV.

4. Duration not to exceed 1 second, one output at a time.

5. Tested initially and after any design or process changes that affect that parameter and, therefore, shall be guaranteed to the limit specified.

6. All pins not being tested are to be open.

7. CMOS levels only tested on CMOS devices. TTL levels only tested on TTL devices.

SYMBOL

PARAMETER

CONDITION

MINIMUM

MAXIMUM

UNIT

Low-level input voltage

TTL

High-level input voltage

TTL

2.2

Low-level input voltage

CMOS

.3*V

High-level input voltage

CMOS

.7*V

Low-level output voltage

= 12.0mA, V

= 4.5V (TTL)

High-level output voltage

= -12.0mA, V

= 4.5V (TTL)

2.4

Low-level output voltage

= 200

µµ

A, V

= 4.5V (CMOS)

+0.05

High-level output voltage

= -200

µµ

A, V

= 4.5V (CMOS)

-0.05

Input leakage current

= V

and V

-10

Three-state output leakage

current

= V

and V

, V

= 5.5V

-10

4,5

Short-circuit output cur-

rent

= 5.5V, V

= V

= 5.5V, V

= 0V

-160

160

5,6

Input capacitance

ƒƒ

=1MHz @0V

I/O

5,6

Bidirectional capacitance

ƒƒ

=1MHz @0V

Supply current: Output

three-state, worst-case pat-

tern programmed,

ƒƒ

MAX1

= 5.5V

120

DDQ

Supply current:

Unprogrammed

= 5.5V

AC CHARACTERISTICS READ CYCLE (Post-Radiation)

1,2

= 5.0V

10%; -55

C < T

< +125

Notes:

1. Post-radiation performance guaranteed at 25

C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

2. Guaranteed by characterization.

3. See page 12 for minimum V

requirements for power-up.

4. Tested initially and after any design or process changes that affect.

5. Device 22VP10-15 tested at -55

C, +25

C and +50

C. At 125

C, tested to 20ns limit.

6. Tested on Programmed Test Ring only.

SYMBOL

PARAMETER

22VP10-15.5

MIN MAX

22VP10-20

MIN MAX

22VP10-25

MIN MAX

UNIT

4,5,6

Input to output propagation delay

15.5

Input to output enable delay

Input to output disable delay

4,6

Clock to output delay

CO2

Clock to combinatorial output delay via internal

registered feedback

4,6

Input or feedback setup time

4,6

Input or feedback hold time

External clock period (t

+ t

)

WH, WL

Clock width, clock high time, clock low time

MAX1

4,6

External maximum frequency (1/(t

+ t

))

MHz

MAX2

4,6

Data path maximum frequency (1/(t

+ t

))

MHz

MAX3

4,6

Internal feedback maximum frequency (1/(t

+ t

))

MHz

Asynchronous reset width

Asynchronous reset recovery time

Input to asynchronous reset

SPR

4,6

Synchronous preset recovery time

4,6

Power up reset time

1.0

INPUT OR

BIDIRECTIONAL

INPUT

COMBINATIONAL

OUTPUT

Combinatorial Output

INPUT OR

BIDIRECTIONAL

INPUT

REGISTERED

OUTPUT

CLOCK

Registered Output

Clock Width

INPUT OR

BIDIRECTIONAL

INPUT

OUTPUT

Combinatorial Output

- 0.5V, V

+ 0.5V)

INPUT ASSERTING

ASYNCHRONOUS

RESET

CLOCK

REGISTERED

OUTPUT

CLOCK

REGISTERED

OUTPUT

INPUT ASSERTING

SYNCHRONOUS

PRESET

SPR

Asynchronous Reset

Synchronous Preset

Notes:

1. V

= 1.5V.

2. Input pulse amplitude 0V to 3.0V.

3. Input rise and fall times 3ns maximum.

Figure 4. AC Electrical

1,2,3