74VHC138
3 TO 8 LINE DECODER (INVERTING)
June 1999
s
HIGH SPEED: t
PD
=5.7 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
µ
A (MAX.) at T
A
= 25
o
C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC138 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC138M
74VHC138T
®
1/8
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
±
20
mA
I
O
DC Output Current
±
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
±
75
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage
2.0 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (see note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
0 to 100
0 to 20
ns/V
ns/V
1) V
IN
from 30% to70%of V
CC
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
V
3.0 to 5.5
0.7V
CC
0.7V
CC
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
V
3.0 to 5.5
0.3V
CC
0.3V
CC
V
OH
High Level Output
Voltage
2.0
I
O
=-50
µ
A
1.9
2.0
1.9
V
3.0
I
O
=-50
µ
A
2.9
3.0
2.9
4.5
I
O
=-50
µ
A
4.4
4.5
4.4
3.0
I
O
=-4 mA
2.58
2.48
4.5
I
O
=-8 mA
3.94
3.8
V
OL
Low Level Output
Voltage
2.0
I
O
=50
µ
A
0.0
0.1
0.1
V
3.0
I
O
=50
µ
A
0.0
0.1
0.1
4.5
I
O
=50
µ
A
0.0
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
4.5
I
O
=8 mA
0.36
0.44
I
I
Input Leakage Current
0 to 5.5
V
I
= 5.5V or GND
±
0.1
±
1.0
µ
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
µ
A
74VHC138
3/8
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
C
IN
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation
Capacitance (note 1)
34
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•
f
IN
+ I
CC
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
V
CC
(V)
C
L
(pF )
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
t
PLH
t
PHL
Propagation Delay
Time
A, B, C to Y
3.3
(*)
15
8.2
11.4
1.0
13.5
ns
3.3
(*)
50
10.0
15.8
1.0
18.0
5.0
(**)
15
5.7
8.1
1.0
9.5
5.0
(**)
50
7.2
10.1
1.0
11.5
t
PLH
t
PHL
Propagation Delay
Time
G1 to Y
3.3
(*)
15
8.1
12.8
1.0
15.0
ns
3.3
(*)
50
10.6
16.3
1.0
18.5
5.0
(**)
15
5.6
8.1
1.0
9.5
5.0
(**)
50
7.1
10.1
1.0
11.5
t
PLH
t
PHL
Propagation Delay
Time
G2A, G2B to Y
3.3
(*)
15
8.2
11.4
1.0
13.5
ns
3.3
(*)
50
10.7
14.9
1.0
17.0
5.0
(**)
15
5.8
8.1
1.0
9.5
5.0
(**)
50
7.3
10.1
1.0
11.5
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5V
±
0.5V
TEST CIRCUIT
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
Ω
)
74VHC138
4/8
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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©
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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