Rev. 2.1
May 2000
1/148
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
ST72334J/N,
ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PRELIMINARY DATA
s
Memories
– 8K or 16K Program memory (ROM or single
voltage FLASH) with read-out protection and
in-situ programming (remote ISP)
– 256 bytes EEPROM Data memory (with read-
out protection option in ROM devices)
– 384 or 512 bytes RAM
s
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Beep and clock-out capabilities
s
Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
s
44 or 32 I/O Ports
– 44 or 32 multifunctional bidirectional I/O lines:
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
s
4 Timers
– Configurable watchdog timer
– Realtime base
– Two 16-bit timers with: 2 input captures (only
one on timer A), 2 output compares (only one
on timer A), External clock input on timer A,
PWM and Pulse generator modes
s
2 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
s
1 Analog Peripheral
– 8-bit ADC with 8 input channels (6 only on
ST72334Jx, not available on ST72124J2)
s
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
s
Development Tools
– Full hardware/software development package
Device Summary
TQFP44
10 x 10
PSDIP42
PSDIP56
TQFP64
14 x 14
Features
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes
8K
8K
16K
8K
16K
8K
16K
8K
16K
RAM (stack) - bytes
384 (256)
384 (256)
512 (256)
384 (256)
512 (256)
384 (256)
512 (256)
384 (256)
512 (256)
EEPROM - bytes
-
-
-
-
-
256
256
256
256
Peripherals
Watchdog, Two 16-bit Timers, SPI, SCI
-
ADC
Operating Supply
3.0V to 5.5 V
CPU Frequency
Up to 8 MHz (with up to 16 MHz oscillator)
Operating Temperature
-40
°
C to +85
°
C (-40
°
C to +105/125
°
C optional)
Packages
TQFP44 / SDIP42
TQFP64 / SDIP56
TQFP44 / SDIP42
TQFP64 / SDIP56
1
Table of Contents
148
2/148
2
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5
ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.6
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7
READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.2
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.3
MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4
CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5
SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 30
9 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1
NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2
EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3
PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table of Contents
3/148
3
11.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 50
13.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
15.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
15.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
15.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
15.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
15.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
15.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
15.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 132
15.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
16 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
16.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
17 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143
17.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
17.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
18 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ST72334J/N, ST72314J/N, ST72124J
4/148
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334
s
8
or
16K
FLASH/ROM
with
In-Situ
Programming and Read-out protection
s
New ADC with a better accuracy and conversion
time
s
New configurable Clock, Reset and Supply
system
s
New power saving mode with real time base:
Active Halt
s
Beep capability on PF1
s
New interrupt source: Clock security system
(CSS) or Main clock controller (MCC)
ST72C334 I/O Configuration and Pinout
s
Same pinout as ST72E331
s
PA6 and PA7 are true open drain I/O ports
without pull-up (same as ST72E331)
s
PA3, PB3, PB4 and PF2 have no pull-up
configuration (all I/Os present on TQFP44)
s
PA5:4, PC3:2, PE7:4 and PF7:6 have high sink
capabilities (20mA on N-buffer, 2mA on P-buffer
and pull-up). On the ST72E331, all these pads
(except PA5:4) were 2mA push-pull pads
without high sink capabilities. PA4 and PA5
were 20mA true open drains.
New Memory Locations in ST72C334
s
20h: MISCR register becomes MISCR1 register
(naming change)
s
29h: new control/status register for the MCC
module
s
2Bh: new control/status register for the Clock,
Reset and Supply control. This register replaces
the WDGSR register keeping the WDOGF flag
compatibility.
s
40h: new MISCR2 register
ST72334J/N, ST72314J/N, ST72124J
5/148
2 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam-
ily. They can be grouped as follows:
– ST72334J/N devices are designed for mid-range
applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.
– ST72314J/N devices target the same range of
applications but without Data EEPROM.
– ST72124J devices are for applications that do
not need Data EEPROM and the ADC peripher-
al.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
The
ST72C334J/N,
ST72C314J/N
and
ST72C124J
versions
feature
single-voltage
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in Section 15 on page 105.
Figure 1. General Block Diagram
8-BIT CORE
ALU
ADDRESS
AND
DATA
BUS
OSC1
ISPSEL
CONTROL
PROGRAM
(8K or 16K Bytes)
V
SS
RESE T
PORT F
PF7,6,4,2:0
(6-BIT)
TIMER A
BEEP
PORT A
RAM
(384 or 512 Bytes)
PORT C
8-BIT ADC
V
DDA
V
SSA
PORT B
PB7:0
PORT E
PE7:0
SCI
TIMER B
PA7:0
PORT D
PD7:0
SPI
PC7:0
(8-BIT)
V
DD
EEPROM
(256 Bytes)
WATCHDOG
MULTI OSC
LVD
OSC2
MEMORY
MCC/RTC
+
CLOCK FILTER
(8-BIT for N versions)
(5-BIT for J versions)
(8-BIT for N versions)
(5-BIT for J versions)
(6-BIT for N versions)
(2-BIT for J versions)
(8-BIT for N versions)
(6-BIT for J versions)
ST72334J/N, ST72314J/N, ST72124J
6/148
3 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout
(N versions)
V
DDA
V
SSA
V
DD_3
V
SS_3
MCO
/
PF0
BEEP
/
PF1
PF2
NC
OCMP1_A
/
PF4
NC
ICAP1_A
/
(HS)
PF6
EXTCLK_A
/
(HS)
PF7
AIN4
/
PD4
AIN5
/
PD5
AIN6
/
PD6
AIN7
/
PD7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24
29 30 31 32
25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ei2
ei3
ei0
ei1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PA1
PA0
PC7 / SS
PC6 / SCK / ISPCLK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
V
SS_0
V
DD_0
V
SS_1
V
DD_1
PA3
PA2
V
DD
_2
OSC1
OSC2
V
SS
_2
NC
NC
RESET
ISPSEL
PA7
(HS)
PA6
(HS)
PA5
(HS)
PA4
(HS)
NC
NC
PE1
/
RDI
PE0
/
TDO
(HS) 20mA high sink capability
ei
x
associated external interrupt vector
ST72334J/N, ST72314J/N, ST72124J
7/148
PIN DESCRIPTION (Cont’d)
Figure 3. 56-Pin SDIP Package Pinout
(N versions)
52
51
50
49
48
47
46
45
44
43
42
41
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
53
54
55
56
PB4
PB5
BEEP / PF1
MCO / PF0
V
SSA
V
DDA
AIN7 / PD7
AIN6 / PD6
AIN5 / PD5
AIN2 / PD2
AIN1 / PD1
AIN0 / PD0
PB7
PB6
AIN4 / PD4
AIN3 / PD3
PB3
PB2
ISPSEL
RESET
V
SS
_2
OSC2
OSC1
V
DD
_2
PE0 / TDO
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0
PB1
PE4 (HS)
PE1 / RDI
ei3
ei0
ei2
ei1
21
20
17
18
19
V
DD_0
EXTCLK_A / (HS) PF7
ICAP1_A / (HS) PF6
OCMP1_A / PF4
PF2
40
39
38
37
36
V
SS_1
PA4 (HS)
PA5 (HS)
PA6 (HS)I
PA7 (HS)
23
22
OCMP2_B / PC0
V
SS_0
28
27
24
25
26
MOSI / PC5
ISPDATA/ MISO / PC4
ICAP1_B / (HS) PC3
ICAP2_B / (HS) PC2
OCMP1_B / PC1
35
34
PA3
V
DD_1
33
32
31
30
29
PC6 / SCK / ISPCLK
PC7 / SS
PA0
PA1
PA2
(HS) 20mA high sink capability
ei
x
associated external interrupt vector
ST72334J/N, ST72314J/N, ST72124J
8/148
PIN DESCRIPTION (Cont’d)
Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts
(J versions)
MCO
/
PF0
BEEP
/
PF1
PF2
OCMP1_A
/
PF4
ICAP1_A
/
(HS)
PF6
EXTCLK_A
/
(HS)
PF7
V
DD_0
V
SS_0
AIN5
/
PD5
V
DDA
V
SSA
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
ei2
ei3
ei0
ei1
PB3
PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
PE1 / RDI
PB0
PB1
PB2
PC6 / SCK / ISPC LK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
V
SS_1
V
DD_1
PA3
PC7 / SS
V
SS
_2
RESET
ISPSEL
PA7
(HS)
PA6
(HS)
PA5
(HS)
PA4
(HS)
PE0
/
TDO
V
DD
_2
OSC1
OSC2
38
37
36
35
34
33
32
31
30
29
28
27
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
39
40
41
42
PB4
AIN0 / PD0
OCMP2_B / PC0
EXTCLK_A / (HS) PF7
ICAP1_A / (HS) PF6
OCMP1_A / PF4
PF2
BEEP / PF1
MCO / PF0
AIN5 / PD5
AIN4 / PD4
AIN3 / PD3
AIN2 / PD2
AIN1 / PD1
V
SSA
V
DDA
PB3
PB2
PA4 (HS)
PA5 (HS)
PA6 (HS)
PA7 (HS)
ISPSEL
RESET
V
SS
_2
V
DD
_2
PE0 / TDO
PE1 / RDI
PB0
PB1
OSC1
OSC2
EI3
ei0
ei2
ei1
21
20
17
18
19
MOSI / PC5
ISPDATA / MISO / PC4
ICAP1_B / (HS) PC3
ICAP2_B/ (HS) PC2
OCMP1_B / PC1
26
25
24
23
22
PC6 / SCK / ISPCLK
PC7 / SS
PA3
V
DD_1
V
SS_1
(HS) 20mA high sink capability
ei
x
associated external interrupt vector
ST72334J/N, ST72314J/N, ST72124J
9/148
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 15 ”ELECTRICAL CHARACTERISTICS” on page
105.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3V
DD
/0.7V
DD
,
C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt
1)
, ana = analog
– Output:
OD = open drain
2)
, PP = push-pull
Refer to Section 11 ”I/O PORTS” on page 37 for more details on the software configuration of the I/O
ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n
°
Pin Name
Type
Level
Port
Main
function
(after
reset)
Alternate function
TQFP64
SDIP56
QFP44
SDIP42
Input
Output
Input
Output
float
wpu
int
ana
OD
PP
1 49
PE4 (HS)
I/O C
T
HS
X
X
X
X
Port E4
2 50
PE5 (HS)
I/O C
T
HS
X
X
X
X
Port E5
3 51
PE6 (HS)
I/O C
T
HS
X
X
X
X
Port E6
4 52
PE7 (HS)
I/O C
T
HS
X
X
X
X
Port E7
5 53 2 39 PB0
I/O
C
T
X
ei2
X
X
Port B0
6 54 3 40 PB1
I/O
C
T
X
ei2
X
X
Port B1
7 55 4 41 PB2
I/O
C
T
X
ei2
X
X
Port B2
8 56 5 42 PB3
I/O
C
T
X
ei2
X
X
Port B3
9
1
6
1
PB4
I/O
C
T
X
ei3
X
X
Port B4
10 2
PB5
I/O
C
T
X
ei3
X
X
Port B5
11 3
PB6
I/O
C
T
X
ei3
X
X
Port B6
12 4
PB7
I/O
C
T
X
ei3
X
X
Port B7
13 5
7
2
PD0/AIN0
I/O
C
T
X
X
X
X
X
Port D0
ADC Analog Input 0
14 6
8
3
PD1/AIN1
I/O
C
T
X
X
X
X
X
Port D1
ADC Analog Input 1
15 7
9
4
PD2/AIN2
I/O
C
T
X
X
X
X
X
Port D2
ADC Analog Input 2
16 8 10 5
PD3/AIN3
I/O
C
T
X
X
X
X
X
Port D3
ADC Analog Input 3
17 9 11 6
PD4/AIN4
I/O
C
T
X
X
X
X
X
Port D4
ADC Analog Input 4
18 10 12 7
PD5/AIN5
I/O
C
T
X
X
X
X
X
Port D5