1
UT54ACS162245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver
Datasheet
March 12, 2003
FEATURES
•
Voltage translation
- 3.3V bus to 2.5V bus
- 2.5V bus to 3.3V bus
•
Cold sparing all pins
•
0.25
µ
Commercial RadHard
TM
CMOS
- Total dose: 300Krad(Si) and 1Mrad(Si)
- Single Event Latchup immune
•
High speed, low power consumption
•
Schmitt trigger inputs to filter noisy signals
•
Cold and Warm Spare - all outputs
•
Available QML Q or V processes
•
Standard Microcircuit Drawing 5962-02543
•
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACS162245S MultiPurpose low voltage
transceiver is built using Aeroflex UTMC’s Commercial
RadHard
TM
epitaxial CMOS technology and is ideal for space
applications. This high speed, low power UT54ACS162245S
low voltage transceiver is designed to perform multiple func-
tions including: asynchronous two-way communication,
Schmitt input buffering, voltage translation, warm and cold
sparing. With V
DD
equal to zero volts, the UT54ACS162245S
outputs and inputs present a minimum impedance of 1M
Ω
mak-
ing it ideal for "cold spare" applications. Balanced outputs and
low "on" output impedance make the UT54ACS162245S well
suited for driving high capacitance loads and low impedance
backplanes. The UT54ACS162245S enables system designers
to interface 2.5 volt CMOS compatible components with 3.3
volt CMOS components. For voltage translation, the A port in-
terfaces with the 2.5 volt bus; the B port interfaces with the 3.3
volt bus. The direction control (DIRx) controls the direction of
data flow. The output enable (OEx) overrides the direction con-
trol and disables both ports. These signals can be driven from
either port A or B. The direction and output enable controls
operate these devices as either two independent 8-bit transceiv-
ers or one 16-bit transceiver.
LOGIC SYMBOL
PIN DESCRIPTION
Pin Names
Description
O Ex
Output Enable Input (Active Low)
DIRx
Direction Control Inputs
xAx
Side A Inputs or 3-State Outputs (2.5V Port)
xBx
Side B Inputs or 3-State Outputs (3.3V Port)
(48)
O E1
G2
(47)
1A1
(46)
1A2
(44)
(2)
1B1
(5)
(3)
1B2
1A3
(43)
1A4
(41)
1A5
(40)
1A6
1B3
(9)
1B6
(8)
1B5
(6)
1B4
(38)
1A7
(37)
1A8
(12)
1B8
(11)
1B7
(1)
DIR1
1EN1 (BA)
1EN2 (AB)
11
12
(25)
O E2
G1
(24)
DIR2
21
22
(36)
2A1
2B1
(13)
(35)
2A2
(33)
2A3
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
(16)
2B2
2B3
(20)
2B6
(19)
2B5
(17)
2B4
(23)
2B8
(22)
2B7
(14)
2EN1 (BA)
2EN2 (AB)
2
PINOUTS
POWER TABLE
When V
DD2
is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic
levels can be applied to all control inputs. For proper operation
connect power to all V
DD
and ground all V
SS
pins (i.e., no float-
ing V
DD
or V
SS
input pins). Tie unused inputs to V
SS
. Always
insure V
DD1
> V
DD2
during operation of the part.
FUNCTION TABLE
COLD/WARM SPARE FUNCTION
The device will place all outputs into a high-impedance state if
either V
DD
supply is taken to zero volts (I
WS
, warm spare), or
if both V
DD
supplies are set to zero volts (I
CS
, cold spare).
DEVICE POWER UP FUNCTION
The device will place all outputs into a high-impedance during
power-up. The high impedance state is maintained for a time
period approximately equal to the rise time of V
DD1
.
1
2
3
4
5
7
6
48
47
46
45
44
42
43
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
OE1
1A1
1A2
V
SS
1A3
VDD2
8
41
1B5
1A5
1A4
9
40
1B6
1A6
10
39
V
SS
V
SS
48-Lead Flatpack
Top View
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
11
12
13
14
15
17
16
18
19
20
V
SS
2B7
2B8
DIR2
21
22
23
24
38
37
36
35
34
32
33
1A7
1A8
2A1
2A2
V
SS
2A4
31
VDD2
2A3
30
2A5
29
2A6
28
V
SS
27
2A7
26
2A8
25
O E2
Port B
Port A
OPERATION
3.3 Volts
2.5 Volts
Voltage Translator
3.3 Volts
3.3 Volts
Non Translating
2.5 Volts
2.5 Volts
Non Translating
ENABLE
O Ex
DIRECTION
DIRx
OPERATION
L
L
B Data To A Bus
L
H
A Data To B Bus
H
X
Isolation
3
LOGIC DIAGRAM
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
(1)
(47)
(48)
(2)
(46)
(3)
(44)
(5)
(43)
(6)
(41)
(8)
(40)
(9)
(38)
(11)
(37)
(12)
1B1
1B2
1B3
1B6
1B5
1B4
1B8
1B7
O E1
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
DIR2
(24)
(36)
(25)
(13)
(35)
(14)
(33)
(16)
(32)
(17)
(30)
(19)
(29)
(20)
(27)
(22)
(26)
(23)
2B1
2B2
2B3
2B6
2B5
2B4
2B8
2B7
OE 2
2.
5V
P
O
R
T
3.
3
V
P
O
R
T
2.
5V
P
O
R
T
3.
3
V
P
O
R
T
4
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent to CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maxim um rating conditions for extended
periods may affect device reliability and performance .
2. For Cold Spare mode (V
DD1
=VSS, V
DD2
=VSS), V
I/O
may be -0.3V to the maximum recommended operating level of V
DD1
+0.3V.
3. Maximum junction temperature may be increased to +175
o
C during burn-in and life test.
DUAL SUPPLY OPERATING CONDITIONS
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL Latchup
>113
MeV-cm
2
/mg
Neutron Fluence
(Note 2)
1.0E14
n/cm
2
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
V
I/O
(Note 2)
Voltage any pin
-.3 to V
DD1
+.3
V
V
DD1
Supply voltage
-0.3 to 4.0
V
V
DD2
Supply voltage
-0.3 to 4.0
V
T
STG
Storage Temperature range
-65 to +150
°
C
T
J
(Note 3)
Maximum junction temperature
+150
°
C
Θ
JC
Thermal resistance junction to case
20
°
C/W
I
I
DC input current
±
10
mA
P
D
Maximum power dissipation
1
W
SYMBOL
PARAMETER
LIMIT
UNITS
V
DD1
Supply voltage
2.3 to 3.6
V
V
DD2
Supply voltage
2.3 to 3.6
V
V
IN
Input voltage any pin
0 to V
DD1
V
T
C
Temperature range
-55 to + 125
°
C
5
DC ELECTRICAL CHARACTERISTICS
1
( -55
°
C < T
C
< +125
°
C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
V
T
+
Schmitt Trigger, positive going
threshold
2
V
DD
from 2.3 to 3.6
.7V
DD
V
V
T
-
Schmitt Trigger, negative going threshold
2
V
DD
from 2.3 to 3.6
.3V
DD
V
V
H1
Schmitt Trigger range of hysteresis
9
V
DD
from 3.0
to 3.6
0.5
V
V
H2
Schmitt Trigger range of hysteresis
9
V
DD
from 2.3 to 2.7
0.4
V
I
IN
Input leakage current
9
V
DD
from 2.7 to 3.6
V
IN
= V
DD
or V
SS
-1
3
µ
A
I
OZ
Three-state output leakage current
9
V
DD
from 2.7 to 3.6
V
IN
= V
DD
or V
SS
-1
3
µ
A
I
CS
Cold sparing input leakage current
3,11
V
IN
= 3.6
V
DD
= V
SS
-5
5
µ
A
I
WS
Warm sparing input leakage current
3,11
V
IN
= V
SS
or
V
DD,
V
DD1
= 0,
V
DD2
= V
DD or
V
DD1 =
V
DD,
V
DD2
= 0
-5
5
µ
A
I
OS1
Short-circuit output current
5, 10
V
O
= V
DD
or V
SS
V
DD
from 3.0 to 3.6
-200
200
mA
I
OS2
Short-circuit output current
5, 10
V
O
= V
DD
or V
SS
V
DD
from 2.3 to 2.7
-100
100
mA
V
OL1
Low-level output voltage
9
I
OL
= 8mA
I
OL
= 100
µ
A
V
DD
= 3.0
0.4
0.2
V
V
OL2
Low-level output voltage
9
I
OL
= 8mA
I
OL
= 100
µ
A
V
DD
= 2.3
0.4
0.2
V
V
OH1
High-level output voltage
9
I
OH
= -8mA
I
OH
= -100
µ
A
V
DD
= 3.0
V
DD
- 0.7
V
DD
- 0.2
V
V
OH2
High-level output voltage
9
I
OH
= -8mA
I
OH
= -100
µ
A
V
DD
= 2.3
V
DD
- 0.7
V
DD
- 0.2
V
6
DC ELECTRICAL CHARACTERISTICS
1
( -55
°
C < T
C
< +125
°
C)
Notes:
1. All specifications valid for radiation dose
≤
1E5 rad (Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
3. All combinations of OEx and DIRx
4. Guaranteed by characterization.
5. Not more than one output may be shorted at a time for maximum duration of one second.
6. Power does not include power contribution of any CMOS output sink current.
7. Power dissipation specified per switching output.
8.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
9.Guaranteed; tested on a sample of pins per device.
10. Supplied as a design limit, but not guaranteed or tested.
11. Zero Volts is defined as 0.0 Volts +/- 0.25Volts.
12. V
DD1
and V
DD2
Voltage rise is monotonic.
13. Rise time measured from V
D D
@ Zero Volts to V
DD
@ greater than 2.3 V.
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
P
total1
Power dissipation
4,6,7
C
L
= 40pF
6.2
mW/
MHz
V
DD
from 3.0V to 3.6V
P
total2
Power dissipation
4,6,7
C
L
= 40pF
3
MHz
V
DD
from 2.3V to 2.7V
I
DD
Standby Supply Current
V
DD1
or V
DD2
V
IN
= V
DD
or V
SS
V
DD
= 3.6V
OE = V
DD
Pre-Rad 25
o
C
10
µ
A
OE = V
DD
Pre-Rad -55
o
C to +125
o
C
475
µ
A
OE = V
DD
Post-Rad 25
o
C
15
mA
C
IN
Input Capacitance
8
f = 1MHz @ 0V
15
pF
V
DD
from 2.3V to 3.6V
C
out
Output Capacitance
8
f = 1MHz @ 0V
15
pF
V
DD
from 2.3V to 3.6V
POR
V
DD1
& V
DD2
Power-On
4,13
V
DD1
or V
DD2
Zero Volt Offset
250
mV
V
DD1
and V
DD2
Rise-Time
12
500
mS
7
AC ELECTRICAL CHARACTERISTICS
1
(Port B = 3.3 Volt, Port A = 2.5 Volt)
(V
DD1
= 3.0V to 3.6V; V
DD2
= 2.3V to 2.7V, -55
°
C < T
C
< +125
°
C)
Notes:
1. All specifications valid for radiation dose
≤
1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
PLH
Propagation delay Data to Bus
2
10
ns
t
PHL
Propagation delay Data to Bus
2
10
ns
t
PZL
Output enable time OEx to Bus
2
12
ns
t
PZH
Output enable time OEx to Bus
2
12
ns
t
PLZ
Output disable time OEx to Bus high impedance
2
15
ns
t
PHZ
Output disable time OEx to Bus high impedance
2
15
ns
t
PZL
2
Output enable time DIRx to Bus
2
12
ns
t
PZH
2
Output enable time DIRx to Bus
2
12
ns
t
PLZ
2
Output disable time DIRx to Bus high impedance
2
15
ns
t
PHZ
2
Output disable time DIRx to Bus high impedance
2
15
ns
t
SLH
3
t
SHL
3
Skew between outputs (40pF +/- 10 pF on each output)
Skew between outputs (40pF +/- 10 pF on each output)
0
0
900
900
ps
ps
t
PLZ
t
PZH
t
PZL
t
PHL
t
PHZ
Propagation Delay
Input
Output
V
DD
V
DD
/2
0V
t
PLH
V
OH
V
OL
V
DD
/2
Control Input
3.3V Output
Normally Low
Enable Disable Times
3.3V Output
Normally High
V
DD
V
DD
/2
0V
V
DD
/2
V
DD
/2
.8V
DD
.2V
DD
V
DD
/2+0.2
V
DD
/2-0.2
.2V
DD
+ .2V
.8V
DD
- .2V
t
PLZ
t
PZH
t
PZL
t
PHZ
2.5V Output
Normally Low
2.5V Output
Normally High
V
DD
/2
V
DD
/2
.7V
DD
.2V
DD
V
DD
/2+0.2
V
DD
/2-0.2
.2V
DD
+ .2V
.7V
DD
- .2V
8
AC ELECTRICAL CHARACTERISTICS
1
(Port A = Port B, 3.3 Volt Operation)
(V
DD1
= 3.0 to 3.6V; V
DD2
= 3.0V to 3.6V, -55
°
C < T
C
< +125
°
C)
Notes:
1. All specifications valid for radiation dose
≤
1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
PLH
Propagation delay Data to Bus
2
7.5
ns
t
PHL
Propagation delay Data to Bus
2
7.5
ns
t
PZL
Output enable time OEx to Bus
2
10
ns
t
PZH
Output enable time OEx to Bus