FEATURES
q 45ns and 55ns maximum address access time
q Asynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
q CMOS compatible inputs, TTL/CMOS compatible output
levels
q Three-state bidirectional data bus
q Low operating and standby current
q Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm
2
/mg
- Latchup immune (LET >100 MeV-cm
2
/mg)
q QML Q and QML V compliant part
q Packaging options:
- 68-lead Flatpack
- 68-pin PGA
q 5-volt operation
q Standard Microcircuit Drawing 5962-96845
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable ( OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
Figure 1. Logic Block Diagram
MEMORY
ARRAY
ROW
SELECT
ROW
SELECT
COL
SEL
COL
SEL
COLUMN
I/O
COLUMN
I/O
R/W
L
CE
L
OE
L
A
11L
A
10L
A
9L
A
0L
R/W
R
CE
R
OE
R
A
11R
A
10R
A
9R
A
0R
I/O
7L
I/O
8L
(7C139)
I/O
7R
I/O
8R
(7C139)
I/O
0L
I/O
0R
ARBITRATION
BUSY
L
BUSY
R
M/S
4
The UT7C138/139 consists of an array of 4K words of 8 or 9
bits of dual-port SRAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. With the M/S pin, the UT7C138/139 can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
WRITE CYCLE
A combination of R/W less than V
IL
(max), and CE less than
V
IL
(max), defines a write cycle. The state of OE is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either OE is greater than V
IH
(min), or
when R/W is less than V
IL
(max).
WRITE OPERATION
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by R/W going high
with CE active. The write pulse width is defined by t
PWE
when
the write is initiated by R/W, and by t
SCE
when the write is
initiated by CE going active. Unless the outputs have been
previously placed in the high-impedance state by OE, the user
must wait t
HZOE
before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated by CE going inactive.
The write pulse width is defined by t
PWE
when the write is
initiated by R/W, and by t
SCE
when the write is initiated by CE
going active. For the R/W initiated write, unless the outputs have
been previously placed in the high-impedance state by OE, the
user must wait t
HZWE
before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
If a location is being written by one port and the opposite port
attempts to read that location, a port-to-port flow through delay
must be met before the data is read on the output. Data will be
valid on the port wishing to read the location (t
BZA
+ t
BDD
) after
the data is written on the other port (see figure 5a).
READ OPERATION
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
ACE
after CE or t
DOE
after OE
is asserted (see figures 3a and 3b).
MASTER/SLAVE
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write
cycle during a contention situation. When presented as a HIGH
input, the M/S pin allows the device to be used as a master and,
therefore, the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave. When presented as a
LOW input, the M/S pin allows the device to be used as a slave,
and, therefore, the BUSY pin is an input.
Table 1. Non-Contending Read/Write
RADIATION HARDNESS
The UT7C138/139 incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide
while maintaining the circuit density and reliability. For
transient radiation hardness and latchup immunity, UTMC
builds all radiation-hardened products on epitaxial wafers using
an advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail
collapse.
Table 2. Radiation Hardness
Design Specifications
1
Notes:
1. The DPRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Not tested for CMOS technology.
INPUTS
OUTPUTS
CE
R/W
OE
I/O
0-7
OPERATION
H
X
X
High Z
Power Down
X
X
H
High Z
I/O Lines
Disabled
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
X
X
---
Illegal
Condition
Total Dose
1.0E6
rads(Si)
LET Threshold
85
MeV-cm
2
/mg
Neutron Fluence
2
3.0E14
n/cm
2
Memory Device
Cross Section @ LET
= 120MeV-cm
2
/mg
< 1.376E
-2
(4Kx8)
< 1.548E
-2
(4Kx9)
cm
2
6
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(V
DD
= 5.0V
±
10%; -55
°
C < T
C
< +125
°
C)
Notes:
* Post-radiation performance guaranteed at 25
°
C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. V
IH
= 5.5V, V
IL
= 0V.
5. I
DD
(OP) derates at 6.4mA/MHz.
6. I
DD
(OP) derates at 3.4mA/MHz.
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
V
IH
High-level input voltage
(CMOS)
0.7V
DD
V
V
IL
Low-level input voltage
(CMOS)
0.3V
DD
V
V
OL
Low-level output voltage
I
OL
= 8mA, V
DD
= 4.5V (TTL)
0.4
V
V
OL
Low-level output voltage
I
OL
= 200
µ
A, V
DD
= 4.5V (CMOS)
0.05
V
V
OH
High-level output voltage
I
OH
= -4mA, V
DD
= 4.5V (TTL)
2.4
V
V
OH
High-level output voltage
I
OH
= -200
µ
A, V
DD
= 4.5V (CMOS)
4.45
V
C
IN
1
Input capacitance
ƒ
= 1MHz @ 0V
25
pF
C
IO
1
Bidirectional I/O capacitance
ƒ
= 1MHz @ 0V
25
pF
I
IN
Input leakage current
V
IN
= V
DD
and V
SS
-10
10
µ
A
I
OZ
Three-state output leakage current
V
O
= V
DD
and V
SS
V
DD
= 5.5V
G = 5.5V
-10
10
µ
A
I
OS
2,3
Short-circuit output current
V
DD
= 5.5V, V
O
= V
DD
V
DD
= 5.5V, V
O
= 0V
-90
90
mA
mA
I
DD
(OP)
4,5
Supply current operating (both ports)
@ 22.2MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
300
mA
I
DD
(OP)
4,6
Supply current operating (single port)
@ 22.2 MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
150
mA
I
DD
(OP)
4,5
Supply current operating (both ports)
@ 18.2MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
275
mA
I
DD
(OP)
4,6
Supply current operating (single port)
@ 18.2 MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
138
mA
I
DD
(SB)
4
Supply current standby
CMOS inputs (I
OUT
= 0)
CE = V
DD
- 0.5,
V
DD
= 5.5V
1
mA
