BCRTMP-1
UT1553 BCRTMP
F
EATURES
p
Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) functions
p
Multiple message processing capability in BC and
RT modes
p
Time tagging and message logging in RT mode
p
Automatic polling and intermessage delay in
BC mode
p
Programmable interrupt scheme and internally
generated interrupt history list
p
Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p
Register-oriented architecture to enhance
programmability
p
DMA memory interface with 64K addressability
p
Eight mode select inputs configure the device for a
wide variety of 1553 protocols: MIL-STD-1553A,
MIL-STD-1553B, McDonnell Douglas A3818,
A5232, A5690, Grumman Aerospace SP-G-151A
p
Comprehensive Built-In-Test (BIT) includes:
Continuous on-line wrap-around test, off-line BIT,
special system wrap-around test
p
Available in 144-pin pingrid array or 132-lead flatpack
packages
p
Standard Microcircuit Drawing 5962-89501 available
- QML Q compliant
16
16
16
CONTROL
DMA/CPU
MESSAGE
RT PROTOCOL
MESSAGE
BC PROTOCOL
HANDLER
INTERRUPT
CONVER-
PARALLEL
SERIAL-TO-
CONVER-
TO-SERIAL
PARALLEL-
MODULE
DECODER
ENCODER/
CHANNEL
DUAL
BUS
TRANSFER
LOGIC
ADDRESS
16
TIMEOUT
TIMRONA
CLOCK &
RESET
12MHz
MASTER
RESET
GENERATOR
ADDRESS
16
1553
HIGH-PRIORITY
RT ADDRESS
STANDARD INTERRUPT
HIGH-PRIORITY
INTERRUPT LOG
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC BLOCK/
STATUS
CONTROL
REGISTERS
LIST POINTER
DATA
16
BUILT-
IN-
TEST
16
16
RT TIMER
INTERRUPT STATUS
INTERRUPT ENABLE
SION
SION
&
HANDLER
&
HANDLER
DATA
CHANNEL
B
1553
DATA
CHANNEL
A
LOGIC
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
RT DESCRIPTOR SPACE
ENABLE
BUILT-IN-TEST
START COMMAND
RESET COMMAND
RESET COMMAND
ACTIVITY STATUS/
OPERATIONAL MODE
PROGRAMMABLE STATUS
W
R
A
P
-A
R
O
U
N
D
T
E
S
T
M
U
L
T
IP
L
E
X
E
R
TIMRONB
Figure 1. BCRTMP BlockDiagram
BCRTMP-2
Table of Contents
1.0
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Features - Bus Controller (BC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Features - Multiple Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0
PIN IDENTIFICATION AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0
INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0
SYSTEM OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5
Legalization Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6
Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.0
REMOTE TERMINAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3
RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.0
BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
BC Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3
BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4
BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5
BC Operational Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.0
MULTIPLE PROTOCOL OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.1 Legalization Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.2 Broadcast Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.3 RT Response Time Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.4 Mode Code Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Status Word Option Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.6 Message Error Technique Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.7 Mode code with Data Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.8 Remote Terminal Time Out Option Select (BC, RT) . . . . . . . . . . . . . . . . . . 43
8.2
Additional UT1553 BCRTMP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.1 DOMC Do Mode Code Control Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.2 Continuous Wrap-Around Circuitry (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.3 Stop Enable (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.4 Forced Busy (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.5 ACTIVE Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.6 Transmitter Inhibit Signals (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.7 Immediate Clear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.8 Status Word Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.0
EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . 46
10.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . 50
11.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.0 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.0 PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
BCRTMP-3
1.0 I
NTRODUCTION
The monolithic CMOS UT1553 BCRTMP provides the
system designer with an intelligent solution to
MIL-STD-1553 multiplexed serial data bus design
problems. The UT1553 BCRTMP is a single-chip device
that implements two of the three defined MIL-STD-1553
functions - Bus Controller and Remote Terminal - and is
flexible enough to conform to many of the MIL-STD-1553
“industry standards” created between and including releases
of MIL-STD-1553A and MIL-STD-1553B. Designed to
reduce host CPU overhead, the BCRTMP’s powerful state
machines automatically execute message transfers, provide
interrupts, and generate status information. The BCRTMP’s
register-based architecture allows it to conform to the many
protocol options regarding status words, mode codes, use
of Broadcast, Message Error, and RT Response Time as
specified in the various “1553 standards.” Multiple registers
offer many programmable functions as well as extensive
information for host use. In the BC mode, the BCRTMP
uses a linked-list message scheme to provide the host with
message chaining capability. The BCRTMP enhances
memory use by supporting variable-size, relocatable data
blocks. In the RT mode, the BCRTMP implements time-
tagging and message history functions. It also supports
multiple (up to 128) message buffering and variable length
messages to any subaddress.
The UT1553 BCRTMP is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRTMP is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTMP, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTMP can use as little or as much memory (up to
64K) as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTMP stores/retrieves, by subaddress, all messages
in the order in which they are transacted.
Sequential Message Status Information
The BCRTMP provides message validity, time-tag, and
word-count information, and stores it sequentially in a
separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that
records, in the order of occurrence, the events that caused
the interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRTMP autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTMP can delay a
host-specified time before executing the next message in
sequence.
Automatic Polling
When polling, the BCRTMP interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTMP
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.
Automatic Retry
The BCRTMP can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTMP can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that
records, in the order of occurrence, the events that caused
the interrupts. The list length is programmable.
Variable Space Allocation
The BCRTMP uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides
flexible data placement and convenient access.
BCRTMP-4
1.3 Features - Multiple Protocol
Since the inception of the loosely defined MIL-STD-1553A
in 1973, various “1553 standards” have developed, all with
their own peculiarities. The UT1553 BCRTMP addresses
MIL-STD-1553A, MIL-STD-1553B, McDonnell Douglas
A3818, McDonnell Douglas A5232, McDonnell Douglas
A5690, and Grumman Aerospace SP-G-151A. While the
part was designed with these “standards” specifically in
mind, the BCRTMP’s flexibility permits conformance to
nearly any conceivable “1553-like standard.” The basic
differences among the various “standards” fall into five
categories:
1) Status Word Definition
2) Mode Code Definition
3) Use of Broadcast
4) Message Error Handling
5) Remote Terminal (RT) Response Time
Status Word Definition
The BCRTMP can operate in a mode where the status word
is defined in strict conformance with MIL-STD-1553B, or
it can operate in a more flexible mode. In this flexible status
word mode, the user can program the individual status word
bits using internal registers.
Mode Code Definition
The designer can place the BCRTMP in an operational mode
so that the device performs in strict conformance with the
mode code definitions for MIL-STD-1553B. The designer
may also opt not to automatically execute mode codes,
providing flexibility in mode code definition and
illegalization.
Use of Broadcast
The BCRTMP has a programmable mode option that allows
the user to determine whether to allow broadcast commands
in a system.
Message Error Handling
Some 1553 protocols (e. g., MIL-STD-1553B) consider any
message error reason to discard the entire message and
suppress status word transmission, while others
(e. g., McDonnell Douglas A3818) define the required
activity according to message error severity. The BCRTMP
can be programmed to conform to either requirement.
Remote Terminal (RT) Response Time
The BCRTMP offers two methods of legalization (Bus
Legalization and DMA Legalization), which the designer
selects depending on the required RT response time.
BCRTMP-5
BUSYACK
Figure 2. BCRTMP Functional Pin Description
D0
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
LGL0
LGL1
LGL2
LGL3
LGL4
LGL5
LGL6
LGL7
LGL8
LGL9
LGL10
RAZ
RAO
RBZ
RBO
TAZ
TAO
TBZ
TBO
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
MCLK
MCLKD2
CLK
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
WRAPEN
WRAPF
ALTWRAP
FBUSY
DMAR
DMAG
DMAGO
DMACK
BURST
TSCTL
BRDCAST
MC
LGLEN
LGLCMD
ERR
DOMC
STDINTL
STDINTP
HPINT
TIMRONA
TIMRONB
COMSTR
SSYSF
BCRTF
CHA/B
TEST
RD
WR
CS
AEN
BCRTSEL
LOCK
EXTOVR
MRST
MEMCSO
MEMCSI
RRD
RWR
DATA
LINES ++
D1
D2
D3
++
++
++
++
ADDRESS
LINES +
MODE
OUTPUTS*
MODE
SELECT
INPUTS**
CLOCK
SIGNALS
POWER
GROUND
WRAP-AROUND
TEST SIGNALS
FORCED BUSY
SIGNALS
DMA
SIGNALS
LEGALIZATION
BUS*
LEGALIZATION
SIGNALS
CONTROL
SIGNALS
STATUS
SIGNALS
TERMINAL
ADDRESS**
BIPHASE IN
BIPHASE OUT
+
+
**
**
**
+
+
*
Pin at high impedance when MRST is low.
**
Pin internally pulled up.
+
Pin at high impedance when not asserted.
++
Bidirectional pin.
***
Formerly MEMWIN.
( )
Pingrid array pin identification in parentheses.
Flatpack pin numbers not in parentheses.
ACTIVE
2.0 P
IN
I
DENTIFICATION
A
ND
D
ESCRIPTION
24
25
26
27
28
29
30
31
36
37
38
39
40
41
42
43
91
92
93
94
95
96
97
102
103
104
105
106
107
108
109
110
23
22
21
20
19
18
17
16
(N6)
(P6)
(P7)
(N7)
(R6)
(R7)
(P8)
(R8)
(R9)
(R10)
(P9)
(P10)
(N10)
(R11)
(R12)
(R13)
14
13
12
11
10
9
8
58
74
3
132
34
67
100
1
33
66
99
6
5
4
(B10)
(B9)
(C9)
(A10)
(A9)
(B8)
(A8)
(A7)
(A6)
(B7)
(B6)
(C6)
(A5)
(A4)
(A3)
(B4)
(R4)
(P5)
(R3)
(N5)
(P4)
(P3)
(P2)
(N3)
(P1)
(N2)
(L3)
(M2)
(N1)
(M1)
(L1)
(K14)
(E15)
(J1)
(H3)
(N9)
(G13)
(C7)
(J3)
(N8)
(H13)
(C8)
(K2)
(J2)
(K1)
(L13)
(M14)
(K13)
(M15)
53
52
57
56
51
50
55
54
44
45
46
47
48
49
82
83
84
85
86
81
90
128
129
89
59
62
63
61
60
87
15
88
7
69
64
70
71
122
123
127
124
125
126
111
112
113
114
115
116
117
118
119
120
121
72
73
78
75
77
76
79
80
(N14)
(P14)
(L14)
(N15)
(P12)
(N11)
(P13)
(R14)
(N12)
(N13)
(C13)
(B14)
(B13)
(B12)
(C11)
(D13)
(C10)
(G1)
(H2)
(A12)
(J14)***
(J15)
(H14)
(K15)
(J13)
(A13)
(M3)
(B11)
(K3)
(G15)
(H15)
(F15)
(G14)
(D1)
(F3)
(F1)
(F2)
(G2)
(G3)
(C5)
(B3)
(A2)
(C4)
(C3)
(B2)
(C2)
(D2)
(E3)
(C1)
(E2)
(F14)
(F13)
(E13)
(D15)
(D14)
(C15)
(C14)
(B15)
**
BCRTMP-6
A0
24
R13
TTB
Bit 0 (LSB) of the Address bus
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
25
26
27
28
29
30
31
36
37
38
39
R12
R11
N10
P10
P9
R10
R9
R8
P8
R7
R6
TTB
TTB
TTB
Bit 1 of the Address bus
Bit 2 of the Address bus
Bit 3 of the Address bus
Bit 4 of the Address bus
Bit 5 of the Address bus
Bit 6 of the Address bus
Bit 7 of the Address bus
Bit 8 of the Address bus
Bit 9 of the Address bus
Bit 10 of the Address bus
Bit 11 of the Address bus
40
N7
A13
A14
41
42
P7
P6
TTO
TTO
TTO
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
A15
43
N6
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
Bit 12 of the Address bus
Bit 13 of the Address bus
Bit 14 of the Address bus
Bit 15 (MSB) of the Address bus
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Legend for TYPE and ACTIVE fields:
TUI = TTL input (pull-up)
AL = Active low
AH = Active high
ZL = Active low - inactive state is high impedance
TI = TTL input
TO = TTL output
TTO = Three-state TTL output
TTB = Bidirectional
Notes:
1. Address and data buses are in the high-impedance state when idle.
2. Flatpack pin numbers are same as LCC.
ADDRESS BUS
BCRTMP-7
TTB
TTB
TTB
TTB
D0
D1
D2
D3
91
B10
92
93
94
B9
C9
A10
Bit 0 (LSB) of the Data bus
Bit 1 of the Data bus
Bit 2 of the Data bus
Bit 3 of the Data bus
D4
D5
D6
D7
D8
D9
D10
D11
95
96
97
102
103
104
105
106
A9
B8
A8
A7
A6
B7
B6
C6
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
Bit 4 of the Data bus
Bit 5 of the Data bus
Bit 6 of the Data bus
Bit 7 of the Data bus
Bit 8 of the Data bus
Bit 9 of the Data bus
Bit 10 of the Data bus
Bit 11 of the Data bus
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
NAME
TYPE
ACTIVE
DESCRIPTION
DATA BUS
D12
D13
D14
D15
107
108
109
110
A5
A4
A3
B4
TTB
TTB
TTB
TTB
Bit 12 of the Data bus
Bit 13 of the Data bus
Bit 14 of the Data bus
Bit 15 (MSB) of the Data bus
--
--
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PIN NUMBER
F/P
PGA
NAME
TYPE
ACTIVE
DESCRIPTION
RTA0
TERMINAL ADDRESS INPUTS
44
P12
TUI
Remote Terminal Address Bit 0 (LSB). The entire
RT address is strobed in at Master Reset. Verify it
by reading the Remote Terminal Address Register.
All the Remote Terminal Address bits are internally
pulled up.
RTA1
45
N11
TUI
Remote Terminal Address Bit 1. This is bit 1 of
the Remote Terminal Address.
RTA2
46
P13
TUI
Remote Terminal Address Bit 2. This is bit 2 of
the Remote Terminal Address.
RTA3
47
R14
TUI
Remote Terminal Address Bit 3. This is bit 3 of
the Remote Terminal Address.
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RTPTY
49
N13
TUI
Remote Terminal (Address) Parity. This is an odd
parity input for the Remote Terminal Address.
RTA4
48
N12
TUI
Remote Terminal Address Bit 4. This is bit 4
(MSB) of the Remote Terminal Address.
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PIN NUMBER
F/P
PGA
BCRTMP-8
61
62
63
K15
J15
H14
TI
TI
TI
AL
AL
AL
AEN
60
J13
TI
AH
BCRTSEL
87
A13
TUI
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LOCK
15
88
M3
B11
TUI
TUI
AH
AL
7
K3
AL