Standard Products
UT69R000 RadHard MicroController
Data Sheet
July 2002
q Harvard architecture
- 64K data space
- 1M instruction space
q High throughput engine
- 2 clocks per instruction
- 8 MIPS @ 16 MHz
- Static design
q 15 levels of interrupts
- 8 external user defined interrupts
- Machine error and power fail
q Two on-board 16-bit interval timers
- Timer A, 10
µ
s/bit
- Timer B, 100
µ
s/bit resolution
q 8-bit software controlled output discrete bus
q Register- oriented architecture has 21
user-accessible registers
- 16-bit or 32-bit register configurations
q Supports direct memory access (DMA) system
configuration
q Built-in 9600 baud UART
q Full military operating temperature range, -55
o
C to
+125
o
C, in accordance with MIL-PRF-38535 for Class Q
or V
q Typical radiation performance:
- Total dose: 1.0E6 rads(Si)
- SEL Immune >100 MeV-cm
2
/mg
- LET
TH
(0.25) = 60 MeV-cm
2
/mg
- Saturated Cross Section (cm
2
) per bit, 1.2E-7
- 2.3E-11 errors/bit-day, Adams to 90%
geosynchronous heavy ion
q Post-radiation AC/DC performance characteristics
guaranteed by MIL-STD-883 Method 1019 testing
at 1.0E6 rads(Si)
q Latchup immune 1.5-micron CMOS, epitaxial,
double-level-metal technology
q Packaging options:
- 132-lead flatpack
- 144-pin pingrid array (plus one index pin)
32
Figure 1. UT69R000 Functional Block Diagram
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
NUI3
STATE1
DI1
DI2
INSTRUCTION
DATA
INSTRUCTION
ADDRESS
MCHNE1
BTERR
MCHNE2
MPROT
PFAIL
INT5
INT6
INT0-4
MRST
20
16
32
32
32
ADD
MUX
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
PROCESSOR
CONTROL
LOGIC
OSCILLATOR
/CLOCK
GENERAL
PURPOSE
REGISTERS
OSCIN
OSCOUT
SYSCLK
ID
IC/ICs
ACC
SHIFT REG
TEMP DEST
32
32
TEMP SRC
BIT REG
32
32
A MUX
B MUX
32-BIT ALU
16
32
16
16
ADDR
MUX
BUS
CONTROL
UART
TBR
RBR
TIMCLK
TES
T
UARTOUT
UARTIN
TR
TB
IM
FR
PI
ST
SW
16
16
16
16
5
16
8
OD(7:0)
OPERAND
DATA
DTACK
M/IO
R/ WR
DS
OPERAND
ADDRESS
PIPELINE
I/O
MUX
INTER-
RUPTS
16
16
16
16
2
Table of Contents
1.0
Introduction..................................................................................................................... 4
1.1 General Description .............................................................................................. 4
1.2 General Operation ................................................................................................. 4
2.0
Register File .................................................................................................................... 6
2.1 General Purpose Registers .................................................................................... 6
2.2 Specialized Registers ............................................................................................ 6
2.2.1 Specialized Register Description ................................................................. 6
3.0
Instruction Port.............................................................................................................. 16
3.1 Instruction Port Operations ................................................................................. 17
3.1.1 STRI Instruction Bus Cycle ....................................................................... 17
3.1.2 LRI Instruction Bus Cycle ......................................................................... 18
4.0
Operand Port ................................................................................................................. 19
4.1 Operand Bus Cycle Operation ............................................................................ 20
4.2 DMA Operation and Bus Arbitration.................................................................. 23
5.0
Discrete Input/Output.................................................................................................... 25
5.1 Output Discrete Bus ............................................................................................ 25
5.2 Discrete Inputs .................................................................................................... 26
6.0
Interrupts ....................................................................................................................... 26
6.1 Interrupt Control ................................................................................................. 26
6.1.1 Interrupt Status........................................................................................... 27
6.1.2 Interrupt Processing and Vectoring ........................................................... 27
6.2 Interrupt Sources................................................................................................. 28
6.3 Interrupt Hardware.............................................................................................. 28
6.4 Interrupt Latency................................................................................................. 28
7.0
Monitor ......................................................................................................................... 28
7.1 Using the Monitor ............................................................................................... 29
7.1.1 Examine Command.................................................................................... 33
7.1.2 Modify Command...................................................................................... 33
7.1.3 Continue Command ................................................................................... 34
7.1.4 Run Command ........................................................................................... 34
8.0
Internal UART Operation ............................................................................................. 34
8.1 UART Transmitter Operation ............................................................................. 34
8.2 UART Receiver Operation.................................................................................. 35
9.0
Programming Interface.................................................................................................. 35
9.1 Data Formats ....................................................................................................... 35
9.2 Instruction Formats ............................................................................................. 36
9.3 Addressing Modes............................................................................................... 37
9.4 Data Movement Operations ................................................................................ 38
10.0 Pin Description.............................................................................................................. 39
11.0 Absolute Maximum....................................................................................................... 46
12.0 Recommended Operating Conditions ........................................................................... 46
13.0 DC Electrical Characteristics ........................................................................................ 47
14.0 AC Electrical Characteristics ........................................................................................ 48
15.0 Packaging ...................................................................................................................... 58
16.0 Ordering ........................................................................................................................ 60
3
DS
R/
M/
DTACK
BGACK
BUSY
BGNT
BRQ
MCHNE1
WE
OE
MRST
INT6
INT5
PFAIL
INT0
INT1
INT2
INT3
INT4
NUI4
TEST
EXCEPTIONS
INTERRUPTS/
INSTRUCTION DATA PORT
OSCIN
OSCOUT
UARTIN
UARTOUT
TIMCLK
UT69R000
RA19
RA18
RA17
RA16
RA15
RA14
RA13
RA12
RA11
RA10
RA9
RA8
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
NUI1
NUI3
BTERR
MCHNE2
MPROT
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
OD7
OD6
OD5
OD4
OD3
OD2
OD1
SYSCLK
INSTRUCTION
ADDRESS
BUS
PROCESSOR
STATUS
OSCILLATOR
UART
DATA BUS
MEMORY
ADDRESS
BUS
CLOCK
OUTPUT
BUS
CONTROL
BUS
ARBITRATION
OD0
Figure 2. UT69R000 Pin Function Diagram
DI1
DI2
STATE1
RD0 - RD15
D0 - D15
OPERAND
OPERAND
NUI2
DISCRETES
WR
IO
4
1.0 Introduction
The UT69R000 is a radiation-hardened high-performance
microcontroller designed, manufactured, and tested to meet
rigorous radiation environments. UTMC designed and
implemented the UT69R000 using an advanced radiation-
hardened twin-well CMOS process. The combination of
radiation-hardness, high throughput, and low power
consumption makes the UT69R000 ideal for high-speed
systems in satellites, missiles, and avionics applications.
1.1 General Description
The UT69R000 is a versatile microcontroller designed to meet
real-time control type applications. Support functions often
found external to a microprocessor are integrated within the
microcontroller. Functions include UART, interval timers, 10
external interrupt vectors, and a 8-bit output discrete bus.
The UT69R000 core (machine) is a two port microcontroller
that accesses instructions from a 1M x 16 instruction port; a
second port (64K x 16 data port) is available for data storage.
Data transfer acknowledge allows the addition of wait states
on the data port. The machine performs overlapping fetches
and executes speeding instruction throughput. A 12 MHz
operating clock frequency provides up to 6 MIPS of
throughput. A later section of this data sheet expands on this
concept.
The UT69R000 architecture is based on 20 16-bit general
purpose registers providing, the programmer with extensive
register support. The UT69R000’s flexibility is enhanced by
the concatenation of 16-bit registers into 32-bit registers. In
addition, all registers are available for use as either the source
or destination for any register operation.
All UT69R000 circuitry is of static design. Internal registers,
counters, and latches do not require refresh as with dynamic
circuit design. Therefore the UT69R000 can operate from DC
to the upper frequency limit of 16 MHz. This type of operation
is especially useful in power critical applications such as
satellites.
The UT69R000 fully supports multiprocessor systems, DMA,
and complex bus arbitration. Bus control passes among bus
masters operating on the same bus. The bus master can be one
of several UT69R000s or any other device requiring DMA.
The UT69R000 supports 15 levels of vectored interrupts. Ten
of these are external interrupts, all of which are user-definable.
All interrupts are serviced in order of priority.
The UT69R000’s three basic instruction formats support 16-
bit and 32-bit instruction. The formats are Register-to-Register,
Register-to-Literal, and Register-to-Long-Immediate
instructions.
Figure 3 shows the UT69R000’s general system architecture.
1.2 General Operation
The UT69R000 reduced instruction set consists of 35 separate
instructions. Most of these instructions execute in two clock
cycles providing high-throughput. The UT69R000 has a
Harvard architecture which incorporates two address and two
data buses. One set of address and data buses interface with
instruction memory (instruction port) and the other interfaces
with data memory (data port). The instruction port consists of
a 20-bit address bus and 16-bit data bus. The maximum
program length of any program is 1 mega-word. The data port
consists of a 16-bit address and data bus, allowing access to
64K x 16 of data storage.
The instruction port is dedicated to the storage of instruction
code; however , two instructions exist that allow the instruction
port manipulation by the machine. These instructions are the
Load Register from Instruction Memory (LRI) and Store
Register to Instruction Memory (STRI).
16
20
16
16
ADDRESS
Figure 3. UT69R000 General System Architecture
CONTROL
DATA
MEMORY
INSTRUCTION
INSTRUCTION
INSTRUCTION
UT69R000
DATA
MEMORY
DATA
ADDRESS
5
The UT69R000 begins operation by first generating an address
on the instruction port; valid data (instruction) is then latched
into the Primary Instruction Register (PIR). After the machine
stores the instruction in the PIR, the machine begins execution
of the instruction in the Instruction Register (IR). If the present
instruction in the IR requires only internal processing, the
machine does not exercise the data bus. If the machine needs
additional data to complete the instruction the machine begins
arbitration for the data port.
Data port arbitration begins with the machine asserting the Bus
Request (BRQ) signal. The machine samples the Bus Grant
(BGNT) and Bus Busy (BUSY) signals on the falling edge of
the clock (OSCIN). When the machine detects that the previous
bus controller has relinquished control of the bus, the machine
generates a Bus Grant Acknowledge (BGACK) signal
signifying that it has taken control of the bus (i.e., data port).
After the UT69R000 takes control of the bus, it generates valid
address and data information. If the machine is interfacing to
slow memory or other peripheral devices that require long
memory-access times, the Data Transfer Acknowledge
(DTACK) signal extends the memory cycle time. By holding
off the assertion of DTACK, the slow device lengthens the
memory cycle until it can provide data for the machine.
The UT69R000 controls the vectoring and prioritizing of
interrupt service. Internal logic selects one of 15 interrupt
vectors, each interrupt vector is allocated four memory
locations. Use the four memory locations to store return from
interrupt service address information along with the interrupt
service routine’s location. The UT69R000 controls prioritizing
of coincident interrupts.
Perform UART control and maintenance via input/output
commands OTR and INR. These commands allow the
programmer to read UART status, and error information, as
well as upload and download information to the receive and
transmit buffers respectively.
Figure 4 shows an example of a system configuration.
INSTRUCTION
DATA
INSTRUCTION
ADD
16
20
NUI3
USER-
DEFINED
SYSTEM
INTERRUPTS
8
UART
I/F
X
C
V
R
GENERAL
PURPOSE
MEMORY
I/O
DEVICE #1
I/O
DEVICE #2
BUS
ARBITER
DMA
DEVICE
#1
1553
I/F
DMA
DEVICE
#2
OP ADD
OP DATA
CONTROL
16
16
6
Figure 4. The UT69R000 Example System Configuration
4
UT69R000
INSTRUCTION MEMORY
CAN ONLY BE ACCESSED
BY THE UT69R000
INSTRUCTION
MEMORY
1M X 16
INTERNALLY
PULLED LOW
SERIAL I/O
BUSY
BGACK
BRQ
BGNT
OE
WE
(MAX)
6
2.0 Register File
The UT69R000 has a register-oriented architecture. The
registers within the machine fall into two categories, general
purpose and specialized registers. All registers are accessible
to the programmer through the instruction set. The programmer
uses data from these registers to perform arithmetic and logical
functions, alter program flow, detect various system and
machine faults, determine machine status, control UART and
timer functions, and for exception handling.
2.1 General Purpose Registers
Figure 5 shows the UT69R000’s 20 general purpose registers.
The UT69R000 normally accesses these registers as single-
word 16-bit registers although the machine can concatenate
these registers into 32-bit double-word register pairs. When the
programmer uses the general purpose registers as a double-
word register pair, the most significant 16 bits of the 32-bit
words are stored in the even-numbered register of the register
pair. For instance, if a 32-bit word is stored in Register Pair
XR6, the most significant word is stored in register R6 and the
least significant word is stored in register R7.
In addition to the 20 general purpose registers, the UT69R000
has a 32-bit accumulator (ACC). The ACC is normally a
destination register, although under certain circumstances it
can be the source register (INR RD, ACC). The accumulator
retains the most significant half of the product during a multiply
instruction or the remainder during a divide operation.
2.2 Specialized Registers
The UT69R000 has 13 special purpose registers. These
registers control machine configuration, report status, and
interrupts. Below is a list of the special purpose registers. The
values in the brackets indicate the power-up condition.
1. Stack Pointer Register (SP) [XXXX (hex)]
2. System Status Register (STATUS) [XXXX (hex)]
3. UART Receiver Buffer Register (RCVR)
[XX00 (hex)]
4. UART Transmitter Buffer Register (TXMT)
[XX00 (hex)]
5. Pending Interrupt Register (PI) [0000 (hex)]
6. Fault Register (FT) [0000 (hex)]
7. Interrupt Mask Register (MK) [XXXX (hex)]
8. Status/Output Discrete Register (SW)
[XXFF (hex)]
9. Instruction Counter Register (IC) [0000 (hex)]
10. Instruction Counter Save Register (ICS)
[XXXXX (hex)]
11. Instruction Register (IR) [0000 (hex)]
12. Timer A (TA) [0000 (hex)]
13. Timer B (TB) [0000 (hex)]
The instruction set provides access to most of the special
purpose registers.
2.2.1 Register Description
Stack Pointer Register
The UT69R000 uses the 16-bit Stack Pointer Register as an
address pointer on PUSH and POP instructions. The machine
pre-increments (POP) and post-decrements (PUSH) the Stack
Pointer contents. The programmer loads and stores the SP by
executing the INR and OTR commands to the stack pointer.
Bit 15 is the most significant bit, the least significant bit is bit
zero.
System Status Register
The System Status Register provides status information on the
UT69R000’s internal operation, including status of the internal
UART. The register is read via the INR Rd, STATUS
instruction. Bit definitions follow.
Figure 5. General Register Set
CONCATENATED 32-BIT
ACC
XR18
XR16
XR14
XR12
XR10
XR8
XR6
XR4
XR2
XR0
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
ACCUMULATOR
R6
R18
R16
R14
R12
R10
R8
R4
R2
R0
REGISTER PAIR
16 BITS
16 BITS
15 14 13 12 11 10 9 8 7
5 4 3 2 1 0
C P Z N V J
I
M
M
E
6
O
E
R
E
F
E
P
E
C
N
T
B
E
T
E
D
R
MSB
LSB
Figure 6. The System Status Register (STATUS)
E
7
Bit Number
Mnemonic
Description
Bit 15
C
Carry. This conditional status is set if a carry is generated
or no borrow. [0]
Carry Equations:
C=
(Dm * Sm * Rm) + (Dm * Sm * Rm)
+(Dm * Sm * Rm)
Where: Dm destination register most significant bit
Sm - source register most significant bit
Rm - result most significant bit (stored in
destination register)
Bit 14
P
Positive. This conditional status is set if the result of an
operation is positive. [0]
Positive Equation: P = N * Z
Bit 13
Z
Zero. This conditional status is set if the result of an
operation is negative. [0]
Zero Equation:Z = Rm * Rm-1 * Rm-2 * R0
Bit 12
N
Negative. This conditional status is set if the result of an
operation is negative. [0]
Negative Equation: N = Rm
Bit 11
V
Overflow. This conditional status is set if the result when an
overflow condition occurs. [0]
Overflow Equation:
V = (Dm * Sm * Rm) + (Dm * Sm * Rm)
Bit 10
J
Normalized. This conditional status is set as the result of a
long instruction and the result is normalized. [0]
Normalized Equation: J = (R32 XOR R31)
Bit 9
IE
Interrupts Enabled. This bit reflects whether interrupts are
disabled or enabled. OTR Rd, ENBL and OTR Rd, DSBL
control this bit and function. [0]
Bit 8
MME
Discrete Input 1. This bit reflects the input stimulus applied
to the input pin.
Bit 7
RE
Receiver Error. This bit is the logical OR combination of the
OE, FE, and PE status bits. [0]
Bit 6
OE
Overrun Error. When active, this bit indicates that at least
one data word was lost because the Data Ready (DR bit 0 of
the Status Register) signal was active twice consecutively
without an INR Rd, RCVR. [0]
8
UART Receiver Register (RCVR)
The UART Receiver Buffer Register (see figure 7) receives
9600-baud asynchronous serial data through the UARTIN
input pin on the UT69R000. Each serial data string contains an
active-low Start bit, eight Data bits, an odd Parity bit, and an
active-high Stop bit. Figure 8 shows a single serial data string.
While receiving a serial data string, the UT69R000 generates
four status flags: Data Ready (DR), Overrun Error (OE),
Framing Error (FE), and Parity Error (PE). The UT69R000
stores these bits in the System Status Register.
Receiver buffer register bits 15-8 are always low. Bit numbers,
7 to 0 (RCD7 - RCD0) contain data the UT69R000 receives
via the serial data port. RCD7 is the MSB; RCD0 is the LSB.
Bit 5
FE
Framing Error. When active, this bit indicates a stop bit was
missing from the serial transmission string. Cleared on next
transmission. [0]
Bit 4
PE
Parity Error. When active, this bit indicates the serial
transmission was received with the incorrect parity. Cleared
on next transmission. [0]
Bit 3
CN
Discrete Input 2. This bit reflects the input stimulus applied
to the input pin.
Bit 2
TBE
UART Transmitter Buffer Empty. This bit indicates the
Transmitter Buffer Register is empty and ready for data. [0]
Bit 1
TE
UART Transmitter Empty. This bit is low while the UART
is transmitting data and goes high when the transmission is
complete. [0]
Bit 0
DR
UART Data Ready. This active-high signal indicates the
UART received a serial data word and this data is available.
Cleared on the execution of INR Rd, RCVR. [0]
Bit Number
Mnemonic
Description
15 14 13 12 11 10 9 8 7
5 4 3 2 1 0
0
5
0
4
0
3
0
2
0
1
0
0
7
0
6
0
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
MSB
LSB
Figure 7. The UART Receiver
Buffer Register (RCVR)
5
4
T
3
R
2
0 1
S
T
D
7
R
C
D
R
C
D
R
C
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
P
A
S
T
O
Figure 8. UART Receiver Single
Serial Data String
P
R
DATA
FLOW
9
UART Transmitter Buffer Register
The UT69R000’s internal UART forms an 11-bit serial string
by combining a Start bit, the eight Data bits from the
Transmitter Buffer Register, an odd Parity bit, and a Stop bit.
Figure 9 shows the composition of the serial data string. The
UT69R000 transmits this serial string through the UARTOUT
pin at a rate of 9600 baud (TIMCLK = 12MHz).
The UT69R000’s internal UART has a double-buffered data
transmission register (figure 10). The UT69R000 first loads
the data for transmission into the Transmitter Buffer Register.
If the UART Transmitter Register is empty, data from the
Transmit Buffer Register automatically transfers to the UART
Transmitter Register. At this time, the TBE bit goes active
indicating more data may be loaded into the Transmit Buffer
Register. This double-buffering scheme allows contiguous
transmission of serial data streams and also decreases the
UT69R000’s required overhead for the UART interface. The
UT69R000 loads the 8-bit Transmit Buffer Register via the
OTR Rd, TXMT instruction.
Two status signals are associated with transmitting serial data.
These signals are the UART Transmitter Buffer Empty (TBE)
and UART Transmitter Register Empty (TE). TBE and TE are
both active high and provide information on the status of double
buffering the UART’s transmitted data. TBE and TE are read
from the System Status Register bits 2 and 1
respectively.
5
4
T
3
R
2
0 1
S
T
D
7
T
X
D
T
X
D
T
X
6
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
P
A
S
T
O
Figure 9. UART Transmitter Data String
P
R
DIRECTION
OF DATA
FLOW OUT
OF THE
UT69R000
Figure 10. The UT69R000 UART Double-Buffered Transmitter Register
REGISTER (OTR) INSTRUCTION
TBR WITH AN OUTPUT
DATA IS LOADED INTO THE
OF THE SYSTEM STATUS
READ FROM BIT 1
TRANSMITTER REGISTER IS
STATUS OF THE UART
8
REGISTER
UART TRANSMITTER
REGISTER (TBR)
UART TRANSMITTER BUFFER
16
DATA BUS
THE UT69R000’s INTERNAL
FROM BIT 2
TBR IS READ
STATUS OF THE
DATA FLOW
DIRECTION OF
T
R
T
S
0
1
2
3
4
5
6
7
X
T
X
T
X
T
X
T
X
T
X
T
X
T
X
T
R
A
P
P
O
T
S
0
1
2
3
4
5
6
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
7
D
X
T
D
C
D
C
D
C
D
C
D
C
D
C
D
C
D
C
OF THE SYSTEM
REGISTER
STATUS REGISTER
10
Pending Interrupt Register
The Pending Interrupt Register (PI) contains information on
pending interrupts attempting to vector the Instruction Counter
Register to a new location. Software or hardware controls the
Pending Interrupt Register contents. Any system interrupt,
when active, sets the corresponding bit in the register. OTR
and INR instruction can also set, clear, and read the Pending
Interrupt Register (figure 11).
Instruction INR Rd, PI stores the PI contents in the destination
register. OTR Rd, PI loads the PI with the contents of the
destination register. OTR Rd, RPI clears the PI register. For
each bit set, to a logic one, in the destination register the
corresponding PI bit is cleared. To clear the PI, first read the
PI, then clear only the bits set to a logic one. Reading, then
clearing the PI prevents the inadvertent clearing of interrupts
occurring during execution of an OTR Rd, RPI command.
Example:
CLEAR: INR Rd, PI
OTR Rd, RPI
To generate a software interrupt clear the corresponding bit in
the PI register before writing to the PI register.
Example:
WRITE: MOV R1, 1000 (hex)
OTR R1, RPI
OTR R1, PI
Note: Do not enable interrupts while the PI is non-zero.
Bit Number
Mnemonic
Description
Bit 15
PWDN
Power Fail
Bit 14