8-BIT MICROCONTROLLER (MCU) WITH ROM, EPROM, OTP AND ON SCREEN DISPLAY (OSD) FOR TV FREQUENCY AND VOLTAGE SYNTHESIS

ST631xx DATASHEET INDEX

Pages

ST63140, ST63142

ST63126, ST63156

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST631xx CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STACK SPACE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

WAIT & STOP MODES

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INPUT/OUTPUT PORTS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . .

SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-BIT VOLTAGE SYNTHESIS TUNING

PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-BIT PWM D/A CONVERTER AND 62.5 kHz OUTPUT FUNCTION . . . . . . . . . . . . . . . .

AFC A/D INPUT, KEYBOARD INPUTS

AND BANDSWITH OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INFRARED INPUT (IRIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PACKAGE MECHANICAL DATA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST63E140/T140, E142/T142

ST63E126/T126, E156/T156

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EPROM/OTP DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PACKAGE MECHANICAL DATA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-BIT HCMOS MCUs FOR

TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD

ST63140, ST63142

ST63126, ST63156

4.5 to 6V operating Range

8MHz Maximum Clock Frequency

User Program ROM:

7948 bytes

Reserved Test ROM:

244 bytes

Data ROM:

user selectable size

Data RAM:

256 bytes

Data EEPROM:

128 bytes

40-Pin Dual in Line Plastic Package for the

ST63126, 156

28-Pin Dual in Line Plastic Package for the

ST63140, 142

Up to 18 software programmable general pur-

pose Inputs/Outputs, including 8 direct LED

driving Outputs

3 Inputs for keyboard scan (KBY0-2)

Up to 4 high voltage outputs (BSW0-3)

Two Timers each including an 8-bit counter with

a 7-bit programmable prescaler

Digital Watchdog Function

Serial Peripheral Interface (SPI) supporting

S-BUS/ I

C BUS and standard serial protocols

Up to Four 6-bit PWM D/A Converters

62.5kHz Output pin

14 bit counter for voltage synthesis tuning

(ST63156, ST63140)

AFC A/D converter with 0.5V resolution

Four interrupt vectors (IRIN/NMI, Timer 1 & 2,

VSYNC.)

On-chip clock oscillator

5 Lines by 15 Characters On-Screen Display

Generator with 128 Characters (2 banks)

All ROM types are supported by pin-to-pin

EPROM and OTP versions.

The development tool of the ST631xx microcon-

trollers consists of the ST63TVS-EMUemulation

and development system to be connected via a

standard RS232 serial line to an MS-DOS Per-

sonal Computer.

This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.

October 1993

PRELIMINARY DATA

DEVICE

ROM

(Bytes)

TUN.

I/O Pins

Package

ST63126

PDIP40

ST63156

PDIP40

ST63140

PDIP28

ST63142

PDIP28

DEVICE SUMMARY

PDIP28

PDIP40

(Ordering Information at the end of the datasheet)

1/82

Figure 1. ST63126, 156 Pin Configuration

Figure 2. ST63140, 142 Pin Configuration

DA0

DA3

PC5 (R)

IRIN

OUT1

DA1

DA2

PA1

(SCL) PB5

(SDA) PB6

(SEN) PB7

KBY2

KBY

KBY0

BSW3

BSW2

BSW0

PA3

PA2

PA4

RESET

OSCin

OSCout

PC1

PA5

PA6

TEST

AFC

(VSYNC) PB2

(HSYNC) PB3

OSDOSCin

OSDOSCout

PC6 (G)

PC7 (B)

VA00282

BSW1

PC3 (BLANK)

PC2 (ON/OFF)

(1)

PC0

DA0

DA3

PC5 (R)

IRIN

OUT1

DA1

DA2

PA1

(SCL) PB5

(SDA) PB6

(SEN) PB7

KBY2

KBY

KBY0

BSW3

BSW2

BSW0

PA3

PA2

PA4

RESET

OSCin

OSCout

PC1

PA5

PA6

TEST

AFC

(VSYNC) PB2

(HSYNC) PB3

OSDOSCin

OSDOSCout

PC6 (G)

PC7 (B)

VA00288

BSW

PC3 (BLANK)

PC2 (ON/OFF)

(1)

BSW0

BSW1

BSW2

KBY0

KBY1

KBY2

OSDOSCout

OSDOSCin

PB3 (HSYNC)

PB2 (VSYNC)

AFC

TEST

PA4

DA0

OUT1

PC6 (G)

PC4

PC3 (BLANK)

PC2

OSCout

OSCin

RESET

PA0

PA1

PA2

VR001389

(1)

BSW0

BSW1

BSW2

KBY0

KBY1

KBY2

OSDOSCout

OSDOSCin

PB3 (HSYNC)

PB2 (VSYNC)

AFC

TEST

PA4

DA0

OUT1

IRIN

PC6 (G)

PC5 (R)

PC4

PC2

OSCout

OSCin

RESET

PA0

PA1

PA2

VR001390

(1)

Note 1. This pin is also the VPP input for EPROM based devices

ST63126

ST63156

ST63140

ST63142

Note 1. This pin is also the VPP input for EPROM based devices

ST63140,142,126,156

2/82

GENERAL DESCRIPTION

The ST63140, 142, 126, 156 microcontrollers are

members of the 8-bit HCMOS ST631xx family, a

series of devices specially oriented to TV applica-

tions. Different ROM size and peripheral configura-

tions are available to give the maximum application

and cost flexibility. All ST631xx members are

based on a building block approach: a common

core is surrounded by a combination of on-chip pe-

ripherals (macrocells) available from a standard li-

brary. These peripherals are designed with the

same Core technology providing full compatibility

and short design time. Many of these macrocells

are specially dedicated to TV applications. The

macrocells of the ST631xx family are: two Timer

peripherals each including an 8-bit counter with a

7-bit software programmable prescaler (Timer), a

digital hardware activated watchdog function

(DHWD), a 14-bit voltage synthesis tuning periph-

eral, a Serial Peripheral Interface (SPI), up to four

6-bit PWM D/A converters, an AFC A/D converter

with 0.5V resolution, an on-screen display (OSD)

with 15 characters per line and 128 characters (in

two banks each of 64 characters). In addition the

following memory resources are available: pro-

gram ROM (7K), data RAM (256 bytes), EEPROM

(128 bytes).

Refer to pin configuration figures and to ST631xx

device summary (Table 1) for the definition of

ST631xx family members and a summary of differ-

ences among the different types.

ST63140,142,126,156

3/82

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

D / A Outputs

TIMER 2

IR INTERRUPT

Input

TEST

TIMER 1

PORT C

PORT B

PORT A

VS output &

AFC Input

ON-SCREEN

DISPLAY

DIGITAL

WATCHDOG/TIMER

SERIAL PERIPHERAL

INTERFACE

OSCin

OSDOSCin

OSDOSCout

OSCout

RESET

R, G, B, BLANK

HSYNC (PB3)

VSYNC (PB2)

VR 01 753E

PA0 - PA7

DA0 - DA3

IRIN/NMI

TEST

AFC & VS

PB2 - PB7

PC0 - PC7

POWER SUPPLY

OSCILLATOR

RESET

8-BIT CORE

USER PROGRAM

ROM

8 KBytes

DATA ROM

USER SELECTABLE

DATA EEPROM

128 Bytes

DATA RAM

256 Bytes

* Refer To Pin Configuration For Additional Information

Figure 3. ST631xx Block Diagram

DEVICE

ROM

(Bytes)

RAM

(Bytes)

EEPROM

(Bytes)

I/O

KBY

I/O

BSW

OUT

AFC

D/A

PACK.

EMUL.

DEVICES

ST63126

256

128

YES

PDIP40

ST63E126

ST63156

256

128

YES

PDIP40

ST63E156

ST63140

256

128

YES

PDIP28

ST6E140

ST63142

256

128

YES

PDIP28

ST63E142

Table 1. Device Summary

ST63140,142,126,156

4/82

PIN DESCRIPTION

and V

. Power is supplied to the MCU using

these two pins. V

is power and V

is the ground

connection.

OSCin, OSCout. These pins are internally con-

nected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow the cor-

rect operation of the MCU with various stabil-

ity/cost trade-offs. The OSCin pin is the input pin,

the OSCout pin is the output pin.

RESET. The active low RESET pin is used to start

the microcontroller to the beginning of its program.

TEST. The TEST pin must be held at V

for nor-

mal operation.

PA0-PA7. These 8 lines are organized as one I/O

port (A). Each line may be configured as either an

input or as an output under software control of the

data direction register. Port A has an open-drain

(12V drive) output configuration with direct LED

driving capability (30mA, 1V).

PB2-PB3, PB5-PB7. These lines are organized as

one I/O port (B). Each line may be configured as

either an input with or without internal pull-up resis-

tor or as an output under software control of the

data direction register. PB2-PB3 have a push-pull

configuration in output mode while PB5-PB7 are

open-drain (5V drive).

PB2 and PB3 lines are connected to the VSYNC

and HSYNC control signals of the OSD cell; to pro-

vide the right signals to the OSD these I/O lines

should be programmed in input mode and the user

can read “on the fly” the state of VSYNC and

HSYNC signals. PB2 is also connected with the

VSYNC Interrupt. The active polarity of VSYNC In-

terrupt signal is software controlled. The active po-

larity of these synchronization input pins to the

OSD macrocell can be selected by the user as

ROM mask option. If the device is specified to have

negative logic inputs, then when these signals are

low the OSD oscillator stops. If the device is speci-

fied to have positive logic inputs, then when these

signals are high the OSD oscillator stops.

PB5, PB6 and PB7 lines, when in output modes,

are “ANDed” with the SPI control signals. PB5 is

connected with the SPI clock signal (SCL), PB6

with the SPI data signal (SDA) while PB7 is con-

nected with SPI enable signal (SEN).

PC0-PC7. These 8 lines are organized as one I/O

port (C). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. PC0-PC2, PC4 have a push-pull con-

figuration in output mode while PC3, PC5-PC7

(OSD signals) are open-drain (5V drive). PC3, PC5 ,

PC6 and PC7 lines when in output mode are

“ANDed” with the character and blank signals of

the OSD cell. PC3 is connected with the OSD

BLANK signal, PC5, PC6 and PC7 with the OSD R,

G and B signals. The active polarity of these sig-

nals can be selected by the user as ROM mask op-

tion. PC2 is also used as TV set ON-OFF switch

(5V drive).

DA0-DA3. These pins are the four PWM D/A out-

puts (with 32kHz repetition) of the 6-bit on-chip D/A

converters. The PWM function can be disabled by

software and these lines can be used as general

purpose open-drain outputs (12V drive).

IRIN. This pin is the external NMI of the MCU.

OUT1. This pin is the 62.5kHz output specially

suited to drive multi-standard chroma processors.

This function can be disabled by software and the

pin can be used as general purpose open-drain

output (12V drive).

BSW0-BSW3. These output pins can be used to

select up to 4 tuning bands. These lines are config-

ured as open-drain outputs (12V drive).

KBY0-KBY2. These pins are input only and can be

used for keyboard scan. They have CMOS thresh-

old levels with Schmitt Trigger and on-chip 100k

Ω

pull-up resistors.

AFC. This is the input of the on-chip 10 level com-

parator that can be used to implement the AFC

function. This pin is an high impedance input able

to withstand signals with a peak amplitude up to

12V.

OSDOSCin, OSDOSCout. These are the On

Screen Display oscillator terminals. An oscillation

capacitor and coil network have to be connected to

provide the right signal to the OSD.

VS. This is the output pin of the on-chip 14-bit volt-

age synthesis tuning cell (VS). The tuning signal

present at this pin gives an approximate resolution

of 40kHz per step over the UHF band. This line is a

push-pull output with standard drive (ST63140,

ST63156 only).

ST63140,142,126,156

5/82

Pin Function

Description

DA0 to DA3

Output, Open-Drain, 12V

BSW0 to BSW3

Output, Open-Drain, 12V

IRIN

Input, Resistive Bias, Schmitt Trigger

AFC

Input, High Impedance, 12V

OUT1

Output, Open-Drain, 12V

KBY0 to KBY2

Input, Pull-up, Schmitt Trigger

R,G,B, BLANK

Output, Open-Drain, 5V

HSYNC, VSYNC

Input, Pull-up, Schmitt Trigger

OSDOSCin

Input, High Impedance

OSDOSCout

Output, Push-Pull

TEST

Input, Pull-Down

OSCin

Input, Resistive Bias, Schmitt Trigger to Reset Logic Only

OSCout

Output, Push-Pull

RESET

Input, Pull-up, Schmitt Trigger Input

Output, Push-Pull

PA0-PA6

I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger, High Drive

PB2-PB3, PB5-PB7

I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger

PB5-PB7

I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger

PC0-PC2, PC4

I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger

PC3, PC5-PC7

I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger

, V

Power Supply Pins

Table 2. Pin Summary

ST63140,142,126,156

6/82

The Core of the ST631xx Family is implemented

independently from the I/O or memory configura-

tion. Consequently, it can be treated as an inde-

pendent central processor communicating with I/O

and memory via internal addresses, data, and con-

trol busses. The in-core communication is ar-

ranged as shown in the following block diagram

figure; the controller being externally linked to both

the reset and the oscillator, while the core is linked

to the dedicated on-chip macrocells peripherals via

the serial data bus and indirectly for interrupt pur-

poses through the control registers.

Registers

The ST631xx Family Core has six registers and

three pairs of flags available to the programmer.

They are shown in Figure 5 and are explained in

the following paragraphs together with the pro-

gram and data memory page registers.

Accumulator (A). The accumulator is an 8-bit

general purpose register used in all arithmetic cal-

culations, logical operations, and data manipula-

tions. The accumulator is addressed in the data

space as RAM location at address FFh .

Accordingly, the ST631xx instruction set can use

the accumulator as any other register of the data

space.

VR001811

PROGRAM

ROM/EPROM

RESET

OPCODE

FLAG

VALUES

CONTROL

SIGNALS

FLAGS

ALU

A-DATA

B-DATA

256

DATA SPACE

DATA

RAM / EEPROM

DATA

ACCUMULATOR

INTERRUPTS

RESULTS TO DATA SPACE ( WRITE LINE )

0,0 1 TO 8MHz

ADDRESS / READ LINE

DEDICATIONS

CONTROLLER

ROM / EPROM

OS Cin

OSCout

ADDRESS

DECODER

Progr am Counter

a nd

6 LAYER STACK

Figure 4. ST631xx Core Block Diagram

SHORT

DIRECT

ADDRESSING

MODE

V REGISTER

W REGISTER

PROGRAM COUNTER

SIX LEVELS

STACK REGISTER

NORMAL FLAGS

INTERRUPT FLAGS

NMI FLAGS

INDEX

VA000423

b11

ACCUMULATOR

Y REG. POINTER

X REG. POINTER

Figure 5. ST631xx Core Programming Model

ST631xx CORE

ST63140,142,126,156

7/82

ST631xx CORE (Continued)

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to the memory locations

in the data space. They are used in the register-in-

direct addressing mode.These registers can be

addressed in the data space as RAM locations at

the 80h (X) and 81h (Y) addresses. They can also

be accessed with the direct, short direct, or bit di-

rect addressing modes. Accordingly, the ST631xx

instruction set can use the indirect registers as any

other register of the data space.

Short Direct Registers (V, W). These two regis-

ters are used to save one byte in short direct ad-

dressing mode. These registers can be addressed

in the data space as RAM locations at the 82h (V)

and 83H (W) addresses. They can also be ac-

cessed with the direct and bit direct addressing

modes. Accordingly, the ST631xx instruction set

can use the short direct registers as any other reg-

ister of the data space.

Program Counter (PC)

The program counter is a 12-bit register that con-

tains the address of the next ROM location to be

processed by the core. This ROM location may be

an opcode, an operand, or an address of operand.

The 12-bit length allows the direct addressing of

4096 bytes in the program space. Nevertheless, if

the program space contains more than 4096 loca-

tions, the further program space can be addressed

by using the Program ROM Page Register. The PC

value is incremented, after it is read for the address

of the current instruction, by sending it through the

ALU, so giving the address of the next byte in the

program. To execute relative jumps the PC and the

offset values are shifted through the ALU, where

they will be added, and the result is shifted back

into the PC. The program counter can be changed

in the following ways:

JP (Jump) instruction.... PC = Jump address

CALL instruction ........... PC= Call address

Relative Branch

instructions ................... PC= PC+offset

Interrupt........................ PC= Interrupt vector

Reset ............................ PC= Reset vector

RET & RETI instructions............ PC=Pop (stack)

Normal instruction ........ PC = PC+1

Flags (C, Z)

The ST631xx Core includes three pairs of flags

that correspond to 3 different modes: normal

mode, interrupt mode and Non-Maskable-Inter-

rupt-Mode. Each pair consists of a CARRY flag

and a ZERO flag. One pair (CN, ZN) is used during

normal operation, one pair is used during the inter-

rupt mode (CI,ZI) and one is used during the not-

maskable interrupt mode (CNMI, ZNMI).

The ST631xx Core uses the pair of flags that corre-

sponds to the actual mode: as soon as an interrupt

(resp. a Non-Maskable-Interrupt) is generated, the

ST631xx Core uses the interrupt flags (resp. the

NMI flags) instead of the normal flags. When the

RETI instruction is executed, the normal flags

(resp. the interrupt flags) are restored if the MCU

was in the normal mode (resp. in the interrupt

mode) before the interrupt. Should be observed

that each flag set can only be addressed in its own

routine (Not-maskable interrupt, normal interrupt

or main routine). The interrupt flags are not cleared

during the context switching and so, they remain in

the state they were at the exit of the last routine

switching.

The Carry flag is set when a carry or a borrow oc-

curs during arithmetic operations, otherwise it is

cleared. The Carry flag is also set to the value of

the bit tested in a bit test instruction, and partici-

pates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic

or logical operation was equal to zero, otherwise it

is cleared.

The switching between these three sets is auto-

matically performed when an NMI, an interrupt and

a RETI instructions occur. As the NMI mode is

automatically selected after the reset of the MCU,

the ST631xx Core uses at first the NMI flags.

ST63140,142,126,156

8/82

ST631xxx CORE (Continued)

Stack

The ST631xx Core includes true LIFO hardware

stack that eliminates the need for a stack pointer.

The stack consists of six separate 12-bit RAM loca-

tions that do not belong to the data space RAM

area. When a subroutine call (or interrupt request)

occurs, the contents of each level is shifted into the

next level while the content of the PC is shifted into

the first level (the value of the sixth level will be

lost). When subroutine or interrupt return occurs

(RET or RETI instructions), the first level register is

shifted back into the PC and the value of each level

is shifted back into the previous level. These two

operating modes are described in Figure 6. Since

the accumulator, as all other data space registers,

is not stored in this stack the handling of this regis-

ters shall be performed inside the subroutine. The

stack pointer will remain in its deepest position, if

more than 6 calls or interrupts are executed, so

that the last return address will be lost. It will also

remain in its highest position if the stack is empty

and a RET or RETI is executed. In this case the

next instruction will be executed.

WHEN CALL

INTERRUPT REQUEST

OCCURS

STACK LEVEL 1

PROGRAM COUNTER

RET OR RETI

WHEN

OCCURS

VA000424

Figure 6. Stack Operation

ST63140,142,126,156

9/82